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jiaotongdeng
- 四路交通灯：压缩文件包括资源有：C语言源代码，四路交通灯原理图，PCB，protues仿真。 是做项目的好资料。-Four-way traffic lights: compressed file including resources: C language source code, four-way traffic light schematic, PCB, protues simulation. Is good information to do the project.
EP1C3_12_1_2_MOTO
- 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
clk
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules.
CLK_V
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用Verilog语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. The use of Verilog language.
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
JIJIAQI
- Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
qiangdaqi
- Quartus II工程压缩文件，是一个典型的基于FPGA的抢答器工程项目，有计数、BCD译码、动态扫描等模块。-Quartus II project files, is a typical browser-based FPGA Answer Project, a count, BCD decoding, dynamic scanning module.
istarVHDL
- 压缩包包含有100个VHDL的程序实例，从简单到复杂有一个渐变的过程，非常适合自学CPLD/FPGA者（使用Verilog HDL者可以不下载）-Compression bags containing 100 examples of VHDL procedures, from the simple to the complex there is a gradual process, and is ideal for learning CPLD/FPGA are (using Verilog HD
msp430f449
- 本压缩包内包含了基于protel99se的msp430f449的实验板原理图，对初学者很有帮助-this is a msp430f449 about tis theroy
examples
- 该压缩文件 是众多基于LINUX下 QT编程 许多初学者 使用的应用程序-examples
single-chipcode
- 单片机密码锁 硬件加程序，无密码压缩，课程设计-Single-chip code lock
alarm-clock
- 该代码用VHDL实现了闹钟的定时和提醒功能。里面包含四部分代码，分别实现了60，30，2分频；键盘控制；外围控制；用quartus2软件就可以打开，压缩包中附有四个代码的仿真结果。-The VHDL code used to achieve the alarm clock to remind the timing and function. Code which contains four parts, namely a frequency 60,30,2 keyboard control
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
correlator
- 代码主要说明了乘积检波器的vhdl描述，同时压缩包中还附带的与之相关的rom,mul4*4乘法器的vhdl描述。 用quartus2软件即可打开使用。-Code shows the main detectors of vhdl product descr iptions, at the same time compressed package also comes with associated rom, mul4* 4 multiplier vhdl descr iption. Quart
Step_ok
- dsp程序 一个很好的程序 基础 没有压缩密码-dsp program
lcd
- 两款LCD驱动源码，IIC接口，可以应用于所有单片机，压缩包中有相关说明资料-Both LCD source driver, IIC interface, can be applied to all single-chip, compressed package relevant descr iptive information
radioTEA5767andCS1000
- 两款不同收音机芯片TEA5767和CS1000的驱动代码，调用接口压缩文档中有说明-Two different radio chip TEA5767 and CS1000 driver code, call the interface described in the document compression
slic_FSK
- 中国电信slic模块中FSK协议的实现源码，压缩包中包含相关说明文档-China Telecom slic agreement module to achieve FSK source, compressed package that contains the relevant documentation
lcdWSM6866A
- 一款LCD芯片的驱动WSM6866A，IIC接口，压缩包中有相关的说明文档-An LCD driver chip WSM6866A, IIC interface, compressed packets are related documentation