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sixuanyi
- 四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
one_in_four
- 用CASE语句来设计的四选一电路,大家可以放心使用的,很简单,也很实用,希望能有所帮助.
VHDL作业－张晓峰036099149
- VHDL的四选一选择器-VHDL four elected a selector
double_mux4_1
- 设计一个双四选一的数据选择器电路 设计要求： （1）双四选一的数据选择器的电路框图如图3.2.3所示，试写出设计块对其逻辑功能进行描述。 -Choose a design of a dual quad data selector circuit design requirements: (1) a double four selected data selector circuit diagram shown in Figure 3.2.3, try to write the
mux4_to_1
- 四选一选择器的Verilog HDL编程，在Quartus II中实现了四选一数据选择器的功能。-Four elected a selector Verilog HDL programming, in the Quartus II in the four election data selector function
4_1
- 四选一编程语言，可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.
bible
- 基于EDA的三八译码器，四选一优先选择器，楼梯开关电路，包含程序运行波形图。-EDA-based decoder of the 38, four elections to choose a priority, and the staircase switch circuit, including wave run.
Desktop
- 四选一多路选择器 modelsim testbench-Select more than one four-way selector modelsim testbench
mux
- 用case描述的 四选一 数据选择器短小精湛初学者必看-With the case described in four short selection of a data selector superb must-see for beginners
7_decoder
- VHDL编写！数据选择器大全！ 包括： mux2to1.vhd 二选一电路 mux2_1.vhd 二选一电路 mux2_1.bdf 二选一电路 mux3to1.vhd 三选一电路 mux3to1_1.vhd 三选一电路 mux4to1.vhd 四选一电路 -VHDL write! Data selector Daquan! Including: mux2to1.vhd two choose a circuit mux2_1.vhd two choose a cir
4
- 双四选一数据选择器74LS153,1、写一个程序，用顺序描述语句和并发描述语句（选择信号代入语句或者条件信号代入语句）分别控制74LS153的一个输出端Q。 2、比较一下顺序语句与并行语句各自的优缺点。 输入：逻辑开关。输出：LED灯。 -A double four election data selector 74LS153, 1, write a program, with sequential and concurrent statements describe the sta
xiao
- 四选一选择器的verilog实现！希望有用-Four selected to achieve a selector verilog! Hope that useful
four_selsect
- 在QuartusII软件环境下，编写的四选一功能的实现，包含仿真波形-Quartusii software in the circumstances, to write a function of the implementation of a simulation waveforms
Multiplexer-Description2
- 通过应用QUARTUSII开发软件对 四选一多路选择器进行设计，并给出运行结果-Software development through the application of QUARTUSII choose one of four multiplexer design, and operating results are given
MUX41a
- 用Verilog HDL编写的四选一选择器，以调试过，可以实现。-Make Verilog HDL
fourone
- 四选一数据表决器，ABCD四选一，选择一个输出端口输出所要的电平。实现数据表决-Four data select a voting machine, ABCD four-pick one, choose an output port to the output level. Data division
verilogfile
- 四选一MUX 电路。作为寄存器或者其他电路的输入选择控制。也是ASIC 设计中的基本门电路之一。-4-1 MUX, used as register or input controller.
fulladder
- 基于Quartus II 的，用VHDL语言编写的四选一电路的设计-Based on the Quartus II, using VHDL language of the four selected a circuit design
mux_4_1
- 在Quartus II中用VHDL语言编写的四选一数据选择器程序-In the Quartus II VHDL language using the four selection procedures for a data selector
mux41
- 四选一数据选择器（四个输入选择一个输出）(Four select a data selector)