搜索资源列表
clk_scan
- 采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1:当按下启动计时按钮时,实验箱上的8个数码管数码1~8以4Hz的频率,从0到9反复不停计数,8个数码管同一时刻显示同一个数字。当按下异步清零按钮时,则8个数码管均显示为0。 电路2:当按下启动计时按钮时,8个数码管1~8以4Hz的频率完成从0到9的跳跃循环计数,即每一时刻只有一个数码管点亮。即:数码管1计数0后,数码管2计数1,以此类推,数码管8计数7后,数码管1再计数8……。当按下异步清零按钮时,则数码管1点亮,显示
LEDxianshi
- 实现数码管的循环计数,数码管接法为共阴级接法。-To achieve the cycle count of the digital control, digital control connection for a total of Yin-class connection.
counter
- 系统循环计数,按键控制 KEY1 停止 KEY2 再动 KEY3 停止 KEY4 清零-System cycle count control KEY1 button again to stop moving KEY3 stop KEY2 Clear KEY4
4segasm
- 4位数码管计数器程序(汇编)循环计数:单片机应用-Counter LED 4 program (compilation)
lcd1602time
- lcd1602时间显示(C语言例程)循环计数-lcd1602 time display (C language routines)
edacounter
- 用VHDL语言编写的计数器,在板子上运行成功,可以循环计数,加减计数,先置数后计数等-Counter with the VHDL language, in the board to run successfully, you can cycle counting, addition and subtraction counting, numbers, counting the first home
cal
- 设计一个十进制计数器,由0到9进行循环计数,同时将计数结果通过数码管显示出来-Design of a decimal counter, from 0 to 9 for cycle counting, while counting resulted in the adoption of digital tube display
counter_99
- Verilog实现的倒计数器,从99到1再循环,编译成功,可以直接运行,是很好的verilog语言的例子-Verilog implementation of the down counter, from 99-1 recycling, compiled successfully, you can directly run, is a good example of verilog language
newproject
- 用来产生循环计数的程序,同时在8位发光二极管上显示相应的计数值。-The procedures used to generate cycle count, while the eight light-emitting diode display the corresponding count.
S2_counter
- 本实验主要是利用开发板上面的数码管实现一个十进制计数器的功能,计数范围 0000-9999,可实现循环计数。-In this study, digital development board above the pipe to achieve a decimal counter, counting range 0000-9999 cycle count.
xuhuanjishu
- 一个2位循环计数的keil 和protues文件-A two loop count keil and protues of files
0000-9999
- 用AT89C51和4个LED数码管显示从0000-9999循环计数-AT89C51 and four LED digital tube display from the 0000-9999 cycle count
alarm
- VHDL,多功能数字钟:具有年、月、日、时、分、秒计数显示功能,以24小时循环计数;具有整点报时功能;可以对年、月、日、时、分及秒进行单独校对,使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for
0-59
- STC89C52的数码管0-59循环计数-STC89C52 digital tube 0-59 cycle counting
Circle_LED
- 流水灯,单片机控制数码管循环计数,在8位流水灯做循环的时候,数码管从0到8显示,到8后回归到0;-Water lights, microcontroller digital control loop count, done in eight light water cycle time, digital tube display from 0-8 to return to after 8 0
include
- 1)设置3个变量,假如A,B,C,其中A在主程序里循环计数,计数间隔为1秒左右(不需要很精确),从0-9循环计数;B在外部中断0程序中计数,计数间隔为1秒左右(不需要很精确),从0计数到9,中断退出;C在外部中断2程序中计数,计数间隔为1秒左右(不需要很精确),从0计数到9,中断退出;外部中断0,1采用下降沿触发,通过按键触发。为了便于观察,P1连接到数码管,P2.0-P2.2对应A,B,C计数选通,每计数一次,将变量输出到数码管上,即在主程序里显示数码管4,在中断0里显示数码管5,在中断1里显
S2_counter_NEW
- 设计一个以十进制为基础的计数器,实现从 0 开始的计数功能;本实验主要是利用开发板上面的数码管实现一个十进制计数器的功能,计数范围0000-9999,可实现循环计数。先输入verilog 程序,然后在 QuartusII 中做波形仿真,通过后下载程序在数码管上查看计数器的功能。-Designing a decimal-based counters, a zero-counting function this experiment is the use of digital control b
at7_ex03
- 使用FPGA内部的PLL产生时钟,计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
stc89c51动态数码管实验
- stc89c51驱动四位数码管 0到100循环计数,并显示到数码管上,4个数码管循环显示,此数码管为共阳数码管(STC89C51 drives four bit digital tube 0 to 100 cycle count, and displays to digital tube, 4 digital tube cycle display, this digital tube is the common Yang digital tube)
程序
- 通过IIC总线协议实现TM1637数码管模块0-100循环计数功能,并设置从0开始 每加数20次,蜂鸣器响1s钟。(The function of 0-100 cycle counting of TM1637 digital tube module is realized by IIC bus protocol, and the buzzer rings 1 s every 20 additions starting from 0.)