搜索资源列表
bstop
- EVM板话音扰码器，使用-D命令展开 C54X带通滤波器汇编文件 -EVM voice scrambler, use-D start C54X order band-pass filter compilation
verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
CPLD_raoma
- 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选
pn_code
- 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog pro
scramble.rar
- 通信用加扰码VHDL电路，解决光传输过程中的连零和连一码的出现。,Communication scrambling circuit VHDL Code
screw
- 一个好用的扰码器，主要用在光纤通信上面。因为为了保持送给光模块的信号不是全1或者全0-A nice scrambler, mainly used in optical fiber communication above. Because in order to maintain the optical module of the signal is not sent to all 1 or all 0
SCRAMBLER
- 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
DATA_scramble
- 扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
CCPCH_DPCH
- WCDMA扰码识别，VHDL语言编写-WCDMA scrambling code identification, VHDL language
82CPLD_raoma
- 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选-CPLD-based code scrambling code and de-scrambling device design, scrambling to achieve with the M series, m series progression and frequency of optional
scr_20
- 完成20位并行数据的伪随机序列扰码，配合解码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 data-parallel pseudo-random sequence scrambling code with the decoding part, improve the SNR of the digital channel. Through integrated simulation, and run specific
descr_20
- 完成20位并行数据的伪随机序列解码，配合扰码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 pseudo-random sequence of parallel data decoding, with part of the scrambling code, and to improve the SNR of the digital channel. Through integrated simulation, an
raoma
- MPSK的matlab仿真中复扰码的生成函数-MPSK matlab simulation of complex scrambling code generating function
scramblee
- 数字对讲机信道编码的扰码和解扰码程序，数字对讲机信道编码的扰码和解扰码程序-scramble and descramble
data_scramble
- 用verilog 语言编译数字通信中的符号扰码，预防长1或长0的出现-a great complied code of data sramble for OFDM
Transmitter
- 基于hdl的ofdm基带处理器发射机的设计与实现 包括 工作时钟 主控单元 导频插入 长短训练序列生成 data符号调制 循环前缀与加窗处理 IFFT/FFT 信道编码 扰码模块等-Hdl of ofdm transmitter baseband processor based design and implementation including work clock master unit pilot insertion length of the training sequence g
SRC_2CH
- 2通道HDCVI视频光端机：实现两个高速AD转换采集HDCVI信号，编码扰码后通过光纤远距离传输，对端收到后解码通过高速DA转换为HDCVI信号。-2 channel HDCVI video Guangduan Ji: two high-speed AD acquisition signal conversion HDCVI, scrambling code via the optical fiber remote transmission, receives an end after deco
Detection0X47
- verilog DVB 扰码设计 0x47-verilog DVB- scrambling design
DATA_Scramble
- 扰码器的FPGA实现，选择的扰码器规格为15位移位寄存器。(FPGA scrambler, scrambler specifications for a 15 bit shift register.)
扰码器Verilog
- 实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)