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Digital-Clock
- 24小时制数字钟，可以简单更改为12小时制-Digital Clock
clock
- 多功能数字钟 含闹钟 时间显示 年 月 日 星期 显示温度-duogongneng shuzizhong
shuzizhong
- 这个是关于用VHDL语言设计出来数字钟的程序，能够实现最基本的功能，对于想学习VHDL语言的人来说，是一个很好练习的例子。-This is about the design using VHDL, digital clock out of the program, to achieve the most basic functions, for people who want to learn VHDL language, it is a good practice example.
topclock
- 基于FPGA的数字钟设计，带有正点报时任意时刻闹钟-Design of FPGA-based digital clock, alarm clock with a punctual timekeeping at any time
SEG7
- 自己设计的数字钟，用6个数码管显示，并且可以调整时间-Digital clock of their own design, with six digital display, and can adjust the time
clock1
- 本程序用VHDL编写数字钟，具有定点报时，手动调整时间等功能，能下载到板子上显示时间。-This program written by VHDL digital clock, with a fixed broadcast, manually adjust the time and other functions, can be downloaded to display the time on the board.
clock
- VHDL编程--数字钟 非常适合初学者-VHDL Programming- digital clock is ideal for beginners
shuzizhong
- 做的一个数字钟 能显示时分秒，功能齐全，用C语言编写的程序，简单易懂，适合大家学习之用。多多支持-A digital clock can be displayed every second, fully functional, with programs written in C language, easy to understand, for all learning. Generous support
clock
- 在FPGA下用VHDL语言设计的数字钟程序-Under the FPGA design using VHDL, digital clock program
jiamshuzihong
- 用8051单片机制作简易数字钟的keil工程文件-Simple digital clock with a single chip made of keil project file
3
- 电子数字钟设计实际上是一个对标准频率（1Hz）进行计数的计数电路。振荡器产生的时钟信号经过分频器形成秒脉冲信号，秒脉冲信号输入计数器进行计数，并把累计结果以“时”、“分”、“秒”的数字显示出来。-Electronic digital clock is actually a standard frequency (1Hz) to count the counting circuit. Oscillator clock signal through the divider formed second
clock
- 该程序是用嵌入式开发的一个多功能数字钟，可以实现正常的计时，倒计时，闹钟，始终调整，整点报时功能-The program is the development of a multi-function embedded digital clock, can achieve a normal time, countdown, alarm clock, and always adjusting, the whole point timekeeping function
timescale-1ns
- 这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。-this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.
shizhong
- vhdl描述的数字钟，功能一样，方法不同-vhdl descr iption of the digital clock, the same function, different methods
shuzizhong
- 《数字钟》的设计。 开机时，显示12：00：00的时间开始计时； P0.0/AD0控制“秒”的调整，每按一次加1秒； P0.1/AD1控制“分”的调整，每按一次加1分； P0.2/AD2控制“时”的调整，每按一次加1个小时； c语言和asm格式都有-" Digital clock" design. Boot, show 12:00:00 time to start timing P0.0/AD0 control " second"
watch
- EDA数字钟VHDL的程序,它分多个模块进行,主要是采用VHDL语言而不是Verlog语言-the program for digital clock of EDA
8952
- 这是一个基于VHDL语言的数字钟设计,它是EDA的一个实例-This is a program for clock ,it is a example for EDA.
rtl
- STOPWATCH,alarm,clock 功能的数字钟-General Digital Clock Clock setting with Switch – Use Key_up and Key_down key to change the number – Use Key_right and Key_left key to change the position – Use set key to start Clock Alarm Function – Use Ala
digi_clock
- 用verilog写的数字钟程序，已在altera公司的cyclone IV开发板上运行成功，很有价值-Digital clock using verilog written procedures for the company in altera cyclone IV development board to run a successful, valuable
shuzhizhong
- 数字钟代码，包括原理图和单片机程序代码。原理图为proteus软件仿真的图片-Digital clock code, including schematic and microcontroller code