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clock
- 在EWB环境下搭建数字钟；有“时”，“分”，“秒”（23小时59分59秒）显示且有校时功能的电子钟； 中小规模集成电路组成的电子钟-EWB environment built in digital clock a " when" , " sub" , " second" (23 hours 59 minutes 59 seconds) shows a timing function and an electronic clock smal
sy6
- 数字钟的VHDL源程序，里面附有数字钟的VHDL源程序和原理图的数字钟电路，数字钟有en,clk,clr等接口。-Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
shuzizhogn
- 数字钟C语言程序，keil开发环境。内含proteus仿真文件。-Digital clock C language program, keil development environment. Containing proteus simulation file.
eclock
- 数字钟 分模块设计 实现基础功能 VHDL编写 -eclock vhdl
FPGAVHDLeclock
- 数字钟设计报告 包括源码 仿真 设计原理等 vhdl编写 -vhdl fpga eclock
timer-key-change
- 本文件为数字钟代码，包含仿真电路图，显示器为数码管，采用动态显示。-failed to translate
vhdlclock
- 数字钟的实现，包括报时，校时，清零，闹钟等功能，内附源文件电路图跟源代码。-This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school.
zhong
- LED数字钟，使用8位数码管显示，中断定时-LED digital clock, using 8-bit digital control, timer interrupt
CLOCK_FINAL
- 8051单片机的数字钟汇编程序，可以实现闹铃-8051 digital clock assembler, can alarm
Counter60sec
- VHDL语言编写的一个六十进制计数器(用于秒)，一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。 -A 60 binary counter（for second） programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total 9 modules that are used to de
Debounce
- VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。该模块相对独立，是学习去抖动的好资料。该模块跟我其它的8个模块配套构成一个数字钟。-Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others and is useful for learning de
Displayer
- VHDL编写的针对八段数码管的显示译码电路。实现动态扫描输出小时、分钟和秒。是基于CPLD开发板设计的一个数字钟的一部分。-Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning method.It is one of my total 9
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
FlashTime
- 用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。 -Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let t
RvsTime
- 用VHDL编写。数字钟校时电路，根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入，每输入一个脉冲，被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impul
ADigCLK
- 用VHDL编写的一个数字钟。该模块是顶层模块，用VHDL例化语句例化各个子模块并组装成一个完整的数字钟。与我的其它8个模块配套构成一个数字钟。 -A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital
complete
- 用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。-With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys,
proteus-simulation-clock
- 以51单片机为控制器，实现数字钟，12864显示，proteus 仿真 模拟时钟-To 51 for the controller chip, digital clock, 12864 show, proteus simulation clock
timer
- 基于单片机的数字钟,基于汇编语言。基于单片机的数字钟,基于汇编语言。-Microcontroller based digital clock, based on assembly language
clock
- 数字钟的实现，其中包括闰年的实现，万年历的实现。-It is very good, but it has something wrong.