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b60jian2
- 60进制减法 相比较 代码效率高 可以进行级联-60 compared to 229 subtraction efficient code can be concatenated
simple_clock_VHDL
- (1)具有时、分、秒计数显示功能，小时为24进制，分钟和秒为60进制。 （2）可以根据需要设置复位、清零、置位等功能。 -(1) with time, minutes and seconds count display, 229 hours for 24, 50 minutes and 60 seconds for the 229. (2) can be reset according to the need, resetting, home spaces, and other fu
Counter
- VHDL硬件描述，使用环境为Quartus2 6.1 分别为16进制及60进制计数器的源代码
CNT60
- 60进制加法器 本人自己编的，已通过老师检验，如有不足之处请多多指教
VHDL1
- 数字电子时钟中，秒和分要求要有60进制计数器和24进制计数器，此为60进制计数器-Digital electronic clock, the seconds and sub-band requires 60 counters and 24-ary counter, this counter is 60 hexadecimal
timer
- 能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有整点报时提示、定时闹钟等功能 -To achieve an hour (24 hexadecimal), minutes and seconds (60 hexadecimal) count function function reset function expansion: with the whole point timekeeping tips, regular features such
24clock
- 实现60进制的计数，每60个脉冲上升沿进一次位。-60 M
wyshizhong
- 24 60 60时钟程序 用VHDL硬件编程语言实现的24进制60进制60进制时钟程序-24 60 60 clock procedures VHDL hardware programming language used to achieve the 24 M 60 M 60 M clock procedures
Shuma
- 完整的电子钟程序，包含报时、定时、闹表的功能，其中包含了二十四进制，60进制计数器的设计，和顶层文件-Complete procedures for the electronic bell, including the time, from time to time, to make the function table, which contains 24 hexadecimal, 60 hexadecimal counter design, and top-level document
code
- modelsim下的60进制计数器源码和测试激励文件-modelsim M counter 60 under the source file and test incentives
cout60
- 用VHDL语言编写的60进制计数器，初学者使用-VHDL language with the 60 binary counter, for beginners to use
multiple_use_clock
- 以数字形式显示时、分、秒时间，十位、个位备用一个数码管显示，分秒为一个60进制计数器，小时为一个“十二翻一”计数器 扩展功能：闹钟、仿电子钟报时、触摸报整点时数和自动报整点时数-clock
paomadenghe60jinzhi
- 一个用VHDL编写的跑马灯程序和60进制计数器的程序，一个是自己设计的一个是老师要求，都在实验箱上验证成功，希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.
jianyishuzizhong
- 一个简易的数字钟，能显示小时、分和秒，是一台按秒计数并显示的计时器，其中秒和分为60进制，小时为24进制计数。-A simple digital clock showing the hours, minutes and seconds, is one count per second and displays the timer, which is divided into 60 seconds, and decimal, hexadecimal count for 24 hours.
shuzizhong
- 数字钟设计，分别由一个24和60进制的计数器及显示模块组成。-It is about a design of digital clock,which is comprised a 24 and a 60 counting device and a display device
vhdl
- 实现60进制计数 二十字街啊？我靠还不够-Count 20 words of 60 binary implementation Street ah? I rely on is not enough
DigitalClock
- 用EDA仿真软件做的一个数字钟设计实验，能够实现小时、分钟、秒的60进制计时。是我的课程设计全部源码哦~-EDA simulation software to do with a digital clock design experiments, to achieve hour, minute, second of 60 Hex timing. Curriculum design is all the source code of my oh
60
- 模为24进制计数器的VHDL语言代码，开发环境可以是Quartus 2软件-24 binary counter module VHDL language code, development environment, Quartus 2 software can be
vhdl-digital-clock
- 数字电子钟VHDL 能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有复位、整点报时提示、定时闹钟等功能 方案： 对数字电子钟的功能进行分析，确定出所需要的各个模块，再通过顶层文件的设计，把各个模块例化综合起来，形成一个完整的电子钟。 -VHDL to implement digital electronic clock hours (24 hex), minutes and seconds (60 decimal) of th
VHDL_60-system_counter
- 用VHDL语言编写的简易60进制的可调节计数器，用于Xilinx ISE软件-A 60-digit system settable countr using VHDL, programming using Xilinx ISE