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  1. FIR_filter_DA_machine

    1下载:
  2. 用verilog 代码编写的179阶FIR数字滤波器,采用分布式算法实现-verilog code used to prepare the 179 band FIR digital filters, using Distributed Algorithms
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:950byte
    • 提供者:a
  1. Distributed+Algorithms

    0下载:
  2. This course is about "distributed algorithms".Distributed algorithms include a wide range of parallel algorithms,which can be classified by a variety of attributes.-This course is about distributed algorithms . Distributed algorithms include a wide
  3. 所属分类:SCM

    • 发布日期:2017-04-09
    • 文件大小:1.67mb
    • 提供者:aple
  1. cannon

    0下载:
  2. cannon 并行程序 Matrix multiplication with the Cannon Algorithm: The matrices A and B are stored in files. The file names have to be specified as parameter. The root process reads the matrices and distributes the respective values to all processes,
  3. 所属分类:SCM

    • 发布日期:2017-03-26
    • 文件大小:1.57kb
    • 提供者:刘铭
  1. vani_tut

    0下载:
  2. A total of 52 files showing examples of shell scr ipting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Dist
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:263.64kb
    • 提供者:Stephen Bishop
  1. DA_fir_parrel

    0下载:
  2. 用FPGA实现并行分布式算法的VHDL程序,采用优化结构实现,功能正确-FPGA implementation using VHDL program parallel and distributed algorithms, realized by optimizing the structure and function correctly
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-22
    • 文件大小:38.08mb
    • 提供者:许磊
  1. FPGA-AND-FIR

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  2. 基于FPGA的FIR滤波器设计与仿真文讨式算法系统的基本原理采用分布式算法-FPGA-based FIR filter design and simulation-type algorithms of the text discuss the basic principles of a distributed algorithm
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:466.51kb
    • 提供者:Jasen
  1. fir_filter_50Mhz

    0下载:
  2. 基于并行分布式算法的高速Fir滤波器的设计代码,采用Verilog编写,压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2014-12-28
    • 文件大小:8.37mb
    • 提供者:Eason
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