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tlv_bare_ifc
- vhdl SOPC solution sram dram uart -vhdl SOPC solution sram Imperial uart
tlv_ide_ifc
- vhdl SOPC solution sram dram uart -2-vhdl SOPC solution sram Imperial uart -2
tlv_pc_ifc
- vhdl SOPC solution sram dram uart 3-vhdl SOPC solution sram Imperial uart 3
arch_pc_ifc
- vhdl SOPC solution sram dram uart 4-vhdl SOPC solution sram Imperial uart 4
BRAM2DRAM
- FPGA内嵌的BRAM资源很少，此代码为DRAM代码风格，可以极大程度上减少FPGA内嵌资源的消耗。txt文档中含源代码，直接粘成vhdl即可
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
dram_controller
- 用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL descr iption Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
DRAMsimManual
- DRAM simulator implemented in verilog/VHDL
VHDL_Sample
- VHDL VGA彩条发射器，里面有4个文件，分别是直接输出的，还有通过ROM查找颜色的，通过RAM和DRAM的-VHDL VGA color of the transmitter, there are 4 files, namely, direct output, as well as to find color by ROM, RAM and DRAM through the