搜索资源列表
lcd_driver
- 用FPGA控制12864液晶输出时钟信息 很好 可以根据自己的需要更改 -12864 LCD control with FPGA clock output information can be very good according to their need to change the
sram_test
- fpga读写SRAM的VERILOG 代码-the verilog code of fpga write/read sram
IIR
- FPGA的IIR算法描述,希望对大家有用-IRR arithetics using fpga
FPGADDS
- dds，FPGA波形发生器,波表，接受，发送-dds, FPGA waveform generator, wave form, to receive, send
1111111
- 16位定点FFT-DSP的FPGA实现-16-bit fixed-point FFT-DSP for FPGA realization
alu_struct
- ALU written in VHDL, tested in FPGA advantage, there will be no support on this code. All right reserved by developer.
fft
- 关于vhdl-FPGA实现fft算法的模块-MATLAB VHDL ADN EDA
TESTRAM
- FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much
URAT_VHDL
- FPGA采用模块工程文件QUARTUS II工程、ADC0809、电机控制PWM、LCD12864显示控制、UART_VHDL-FPGA module QUARTUS II project engineering documents, ADC0809, motor control PWM, LCD12864 display control, UART_VHDL
ADC0809_VHDL_QUAARTUSII_PROJECT
- FPGA模块工程、ADC0809状态机控制ADC0809_VHDL_QUAARTUSII_PROJECT可以直接使用！-FPGA module works, ADC0809 control state machine can be used directly ADC0809_VHDL_QUAARTUSII_PROJECT!
fpga_tcl
- Altera FPGA的特殊管脚的连接(中文).doc TCL_教程.pdf-Altera FPGA tcl
fpganios
- fpga制作的逻辑分析仪 nios2控制系统 自己的科创论文 绝对有用-produced fpga logic analyzer control system nios2 Branch' s own record is absolutely useful papers
EXAMPLs
- 康芯公司FPGA开发板的 一些资料 有cpu8051IP核-Kang FPGA development board core company information cpu8051IP some nuclear
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
aesencryption
- Aes encryption on Fpga
dds_1024
- fpga实现DDS，1024个点，已通过Q2综合，绝对好用-fpga achieve DDS, 1024 points have been integrated through Q2, the absolute ease of use
fifo_test.v.tar
- code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
LCD_Top
- FPGA 的verilog LCD显示代码-FPGA code in verilog LCD display
timing_design_of_fpga
- 主要是,fpga,cpld设计时的时序设计需要注意和考虑的问题-Mainly, fpga, cpld design design need to pay attention to the timing of the issue and consider