搜索资源列表
gff_int_mul
- application of a galois field multiplication and normal multiplication
c17_GF_multiple.rar
- 精通verilog HDL语言编程源码之3--伽罗华域乘法器设计,Proficient in language programming verilog HDL source of 3- Galois field multiplier design
GFverilog-hdl
- 伽罗华域的乘法器的设计，使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
GaloisFields
- Galois Field Arithmetic algorithm
Galois_field_multiplier_verilog_design
- 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
GFMultiplication
- its on galois field multiplication
GAFF
- 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
mix
- 本代码是基于Verilog语言，是在伽罗瓦域GF(2^8)上完成加法和乘法运算，主要完成ASE加密的列混合运算-This code is based on the Verilog language, is the Galois field GF (2 ^ 8) on the completion of addition and multiplication, the main column of the completion of ASE encryption hybrid operation
ff_mul
- 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
GFPGFR
- Code Composer Studio中加罗华域乘法的实现-The implementation of CCS in the Galois field multiplication
mul
- 伽罗华域GF（q）乘法器 有详细的步骤-Galois field ( q ) multiplierer
hash
- 基于伽罗瓦域的ghash核，用于GCM。其中，128位伽罗瓦域乘法器使用的是多项式算法。经验证，可综合，供参考。-Galois field based on the nuclear ghash
Tate_Bilinear_Pairing_latest.tar
- The Tate Bilinear Pairing core is for calculating Tate bilinear pairing especially on super-singular elliptic curve in affine coordinates defined over a Galois field , whose irreducible polynomial is . (For improving security, an irreducible po
chengfaqi
- 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
RS
- 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS
GF乘法器
- 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)