搜索资源列表
FPGAJPEGCODING
- motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．-motionjpeg FPGA Coding, a bit old, but the reference. Some things and h.264 is roughly the same.
codeupload
- 上传源码文件为配合SeedVPM642板视频开发，从合众达公司购买的最新的源码库 除源码外，均配有使用说明,我已经搜索过，贵站应该没有相同的代码 在源码最后，上载了H.264标准白皮书 编译环境为CCS index 1.边缘检测程序(new) 2.运动检测程序 3.PC_VPM642 双向通信例程（TCPIP） 4.SEEDVPM642_loop(同步) 5.SEEDVPM642_loop3G2_图象拼接 希望站长能够开通我的会员帐号，谢谢
arm-download-98665.rar
- The OpenMAX DL (Development Layer) APIs contain a comprehensive set of audio, video, signal processing function primitives which can be implemented and optimized on various CPUs and hardware engines and then used for accelerated codec functionality.
s3c6410-h264-IDR-encode-ok
- 这是上一个代码的优化，加了IDR帧编码，适合不稳定网络（如移动通信网），已产品化，基于华恒S3C6410-R2开发板采集视频并压缩为H264格式，带IDR帧，使用时.c文件要改名为cam2fb.c-This is a code optimization, plus the IDR frame coding for unstable networks (such as mobile communications network), has been product oriented, huahen
S3C6410_datasheet_H.264
- 主要包括s3c6410的datasheet，并包括在6410芯片上的Android平台H.264的解码流程，包括读取h.264文件，到输出到LCD.对于做基于android的视频的朋友还是有帮助的！-Including s3c6410 the datasheet, and included in the 6410 chip to decode H.264 Android platform process, including reading the h.264 file to output to
GM8180_Block_Data_Sheet_V1.1
- GM8180 H.264/MPEG CODEC PLATFORM S O C GM8160/GM8180 video chip with FA626 CPU core provides a high performance solution to accelerate the image and video related applications such as the H.264, MPEG4, and JPEG to the end products
Hi3510_CN
- Hi3510内部有一个ARM9的处理器，该产品一经推出就在市场引起很大的震动，虽然现阶段Hi3510在D1的处理方面还有些不成熟，但是由于是标准H.264的产品，相信在市场方面会逐步获得行业的认可-Hi3510 internal an ARM9 processor, the product, once introduced in the market created a big shock, although at this stage D1 of the processing in the H
SecureFileTransfer
- 一个安全文件传输的项目资料，用到的用H.264算法，网络加密算法等等里面有详细的项目文档和项目实例，已经在产品中得到应用-A secure file transfer program, as used with the H.264 algorithm, encryption algorithm, etc. inside the network detailed project documents and project examples, has been applied in the prod
H[mm.264
- 这是一个描述的文档，教你怎么写Verilog关于H264 的文章那个，考了非常受启发。-This is a descr iption of the document, teach you how to write Verilog that the article on the H264, the test is very enlightening.
AnEfficientDouble-FilterHardwareArchitectureforH.2
- 在此提出了一種新穎的硬體結構 實時執行的自適應去塊效應 過濾過程中指定的H.264/AVC視頻編碼 標準。-In this paper,a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented.The deb
DSP_h264_VariableBlockSize
- 這是用verilog HDL實現H.264可變block大小的源碼。為了使其能在FPGA上運作，還加入了我自己的改善。-A verilog HDL code for H.264 with variable block size and my own improvement.
nova_latest.tar
- VERILOG source code of a H.264 baseline decoder.
mc_t
- 利用verilog实现H.264中半像素插值功能。30个周期完成一个4x4块儿的横向、纵向和斜向的插值。-Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
mc
- 通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
Cabad
- MPEG-4/AVC - H.264 CABAC decoder written in VHDL and synthesis on a Virtex 5
01.-H.264-CIF-Demo-via-PCI_v2.0
- 实现4路CIF格式视频DSP端H.264 v1.1编码，然后通过PCI以流方式传送到PC机解码并实时播放.-Achieve 4 CIF format video encoding H.264 v1.1 DSP side, and then transmitted through the PCI stream to a PC real-time decoding and playback.
05.-H.264-D1-Loopback-Demo_v2.0
- 实现1路D1格式视频DSP端采集、h.264 v2.0编码、h.264 v2.0解码和视频输出回放显示。 -Way to achieve a D1-format video DSP-side collection, h.264 v2.0 encoding, h.264 v2.0 decoding and playback of video output display.
RTP_h_264
- RTP 协议是IETF ( Internet Engineering TaskFo rce) 在RFC1889 中给出的, 是专门为交互式音频、视频、仿真数据等实时媒体应用而设计的轻型传输协议。RTP 被定义为在一对一或一对多的传输情况下工作, 其目的是提供时间信息和实现流同步。RTP 通常使用UDP来传送数据, 但RTP 也可以在TCP 或A TM 等协议下工作.对H.264网络开发有何大帮助- The RTP protocol is given in RFC1889 by IETF (I
H.264_on_BF561
- 这是一段H.264的源代码，这段代码在BF561上移植成功-This is a H.264 source code, this code is successfully transplanted in BF561
buffer
- Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA