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CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
xilinxise10.1edk
- Xilinx ise10.1 edk 使详解 xilinx培训资料 中文翻译过的华为培训资料 以Spartan3为例-Xilinx ise10.1 edk Xiangjie xilinx training materials to the Chinese translated example of Huawei training materials to Spartan3
edk_ctt
- xiinx的edk开发的文档，看了这个文档，你可以找到所有xilinx EDK开发的相关文档。-xilinx edk development document,ISE10
picoblaze_test_700AN
- Xilinx PicoBlaze application developed in ISE10.1.3.
CORDIC_SINE
- 在ISE10.0下的CORDIC算法产生正弦波，可控制其幅度等参数-Under the CORDIC algorithm in the ISE10.0 produce sine wave, its amplitude and other parameters can be controlled
tutorial
- 计数器 平台：Xilinx ise 10.1 说明：和ise10.1快速帮助手册配套的源码，适用于初学者。-counter platform: Xilinx ise 10.1 comment: supplement to ise quick start tutorial 10.1, suitable for freshman to fpga and ise software.
Lab6
- 采用ISE10.1，VHDL语言数字时钟的设计，压缩包为源程序代码-By ISE10.1, VHDL language digital clock design, source code for the compressed
paodan101
- 北京市电子设计大赛 完整工程 ISE10.1-ISE 10.1
comp4
- 用verilog编了一个比较器，开发环境是xilinx ise10.1-Verilog compiled using a comparator, the development environment is the xilinx ise10.1
decode3_8
- 用verilog编写的三八译码器的演示程序，编程环境是xinlinx ise10.1-March Eighth prepared with verilog decoder demo, programming environment is xinlinx ise10.1
adder4
- 这是一个用verilog编写的四位加法器，编程环境是xilinx ise10.1.-This is a written with the four adder verilog, programming environment is xilinx ise10.1.
gate
- 用verilog编写，与或非门的演示程序，编程环境是xilinx ise10.1.-Prepared using verilog, or non-doors demo program with the programming environment is the xilinx ise10.1.
gj-2s
- 基于赛灵思EXCD-1的FPGA开发板，使用ISE10.1开发环境，使用VHDL语言编写，功能为计算输入方波的频率。输入方波，输出方波的频率，用数码管显示，每2s更新一次。管脚配置见工程。-Based on the FPGA Xilinx EXCD-1 development board, using ISE10.1 development environment, using the VHDL language, functions for calculating the frequency
fifo_chipscope
- 学习FIFO的初级资料，代码工程在ISE10.1上运行，还有在线示波器chipscope的步骤指导哦！-Study of the primary data FIFO, the code works ISE10.1 run, there is scope chipscope step online guide Oh!
cla16
- 16位超前进位加法器的源代码，整个工程文件都有，是在ISE10.1下建立的，可以帮助理解超前进位原理（对了，是Verilog的，因为上面没看到只好选VHDL了）-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
led_rotate
- 这个是我近期自己在Spartan3E上面写的一个用开发板上的旋钮控制LED灯的流向，可顺时针逆时针，按下旋钮灯灭，开发环境ISE10.1-This is my own Spartan3E write recently, a development board with a knob control the flow of LED lights can be clockwise, counterclockwise, press the knob to the lamp, and the devel
ISE10.1manuals
- ise10.1的说明书，希望学习fpga的朋友，希望能给朋友们带来帮助-Ise10.1 s instructions, wish to learn the fpga friends, hope to bring help to friends
ISE10.1-introducement
- 文档介绍了使用ISE10.1进行某种功能的FPGA操作步骤，包括从新建文档、综合、功能仿真、编译实现和插入IP核等步骤，讲解非常详细。-Document ISE10.1 introduces the function of some kind of FPGA procedures, including from new document, comprehensive, function simulation, compile realization and insert the IP nucle
ISE10.1
- xilinx ISE10.1开发环境指南，叫你如何操作ISE10.1-xilinx ISE10.1