verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.

ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker