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UART 源码 (lattice version)
- UART 源码 (lattice version)-UART source (lattice version)
并口的CPLD烧录线,通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)
- 并口的CPLD烧录线,通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
ispLEVER是LATTICE的CPLD、FPGA继承开发环境
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境,ISPLEVER许可文件--ISPLEVER6.0-7.1的注册机,ispLEVER is LATTICE of CPLD, FPGA development environment succession, ISPLEVER license file- ISPLEVER6 .0-7.1 the Zhuceji
sdram_vhdl_lattice.rar
- lattice sdram 控制器VHDL源代码,Sound code of Lattice Sdram Controller based on VHDL
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8,开放所有源代码,包括VHDL,编译器,支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp
music
- 设计并调试好一个能产生”梁祝”曲子的音乐发生器,并用EDA实验开发系统(拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ,FLEX10K系列的EPF10K10LC84-3 FPGA, ACEX1K系列的 EP1K30 FPGA,Xinlinx 的XC9500系列的XC95108 CPLD,Lattice的ispLSI1000系列的1032E CPLD)进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率,对其进行各种分频
ISPDownload
- 下载线大全,Xilinx,Altera,ARM,AVR,S52,Lattice-Download Line Book, Xilinx, Altera, ARM, AVR, S52, Lattice
DDR_SDRAM
- ddr sdram 的控制程序,lattice的,比较好用的,大家-ddr sdram control program, lattice, and relatively easy to use, and we look
UART_VHDL_Verilog_Lattice
- 本压缩包中含有串口程序的VHDL,Verilog,Lattice三种版本的代码,均已实现。在压缩包中,含有非常详细的串口的实现规格。各种版本的代码中,含有完成的源文件,测试文件,模拟文件。-This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains
Latticescreen
- 51单片机C语言多种点阵屏驱动程序(开发软件为keil C ---8字点阵屏左移程序,64_16点阵屏驱动程序,上移显示程序,左移显示程序)51 monolithic integrated circuit C language many kinds of lattice screen driver (develops the software is keil C ---8 character lattice screen left shift procedure, the 64_16 latti
colorful_signal
- 设计并调试好一个VGA彩条信号发生器,并用EDA实验开发系统(拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ,FLEX10K系列的EPF10K10LC84-3 FPGA, ACEX1K系列的 EP1K30 FPGA,Xinlinx 的XC9500系列的XC95108 CPLD,Lattice的ispLSI1000系列的1032E CPLD)进行硬件验证。 设计思路 由系统提供的时钟源引入扫描信号,根据VGA彩色显示器的工作原理,设计出各种颜色编码
lattice
- 本程序是用VHDL编写,用于实现点阵显示功能。-This procedure is used VHDL to prepare for the realization of dot-matrix display.
A01
- 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilin
olb-0.5r1
- open source lattice boltzma-open source lattice boltzmann
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
ISPDownload
- protel99文件,下载电缆SCH及PCB(包括LATTICE ALTERA ARM AVR XILINX S52)-protel99 file, download cable sch and pcb (include : LATTICE ALTERA ARM AVR XILINX S52)
gexingjiegou
- 对格型滤波器进行了算法仿真,功能实现良好,我以仿真通过,请放心下载使用-Of the lattice filter algorithm for the simulation, the functional to achieve a good simulation through I, please rest assured that download
Lattice-Machxo-FPGA-Loader
- Application note (source code + documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.-Application note (source code+ documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP progra
VHDL-FPGA-xilinx-altera-frily
- VHDL的经典经验。相当的不错,一个多年开发FPGA的工程师自己的记录,适用于ALTERA,XILINX,LATTICE等FPGA的开发。希望对大家有用。-VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera
Three-Dimensional-Lattice-Boltzmann-Model-for-Hig
- Three-Dimensional Lattice Boltzmann Model for High-Speed Compressible Flows