搜索资源列表
TIDM642DSPforCMOS
- TI DM642 DSP 驱动CMOS 成像芯片MT9T001(Micron)源代码,TI原版资料.包含驱动环境配置,对如基于DSP的数码相机,摄像机开发有重要参考价值.-TI DM642 DSP-driven CMOS imaging chip MT9T001 (Micron) source code, TI original information. It includes driving environment, such as the DSP-based digital cameras,
sdram_verilog
- 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
xapp134_vhdl
- The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.
SENSOR11111.rar
- 美光的摄像头sensor MT9D131的原理图,Micron camera sensor MT9D131 the schematic diagram
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
MT9M131_PB.rar
- Datasheet for Micron MT9M131 CMOS sensor.,Datasheet for Micron MT9M131 CMOS sensor.
NandFlash-FPGA-controller(ECC)
- 该压缩包包括NAND FLASH（美光）的FPGA控制器的原理及VHDL源码，非常具有参考价值。-The archive includes NAND FLASH (Micron) the principle of the FPGA and VHDL source code control, very valuable reference.
verilog_sdram_controller_testbench
- SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
verilog_sdram
- SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim
micron_sdram_simulation_model
- micron各种规格的SDRAM的仿真模型及详细设计资料，基于verilog语言。-micron variety of SDRAM simulation model and detailed design information, based on the verilog language.
sdram_models
- MICRON公司SDRAM的各种仿真模型，可以用于各种仿真环境-sdram simulation model
m73a_nand_model
- Micron公司m73a系列nand flash仿真模型及测试文件-micron m73a series nand flash simulation model and testbench
MI-1310
- 镁光cmos sensor mt9m111 的 i2c 初始化代码-Micron cmos sensor mt9m111 the i2c initialization code
webCam-FPGA
- 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
c_xapp454
- 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and t
NAND_IO_x16
- Nand IO C code - Micron
Micron
- Micron is a list of tools for win ce 5.0
sdram_vhd_134
- Design Descr iption: The SDRAM controller is designed for a Virtex device. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz. For a full functional descr iption see Application Note 134: h
mt48lc4m16a2
- 模拟micron的sdram的 VHDL 代码，用于验证自己的sdram控制器。-Micron sdram the VHDL simulation of the code used to validate their sdram controller.
micron-lpddr-sdram-lpddr_model
- modelsim，micron公司的ddr sdram仿真模型，verilog。-modelsim，micron，ddr sdram simulat module，verilog。