搜索资源列表
rs-5-3
- 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字
RSdecoder.rar
- cpld/fpga RS(204,188)译码器的verilog程序,cpld/fpga RS (204,188) decoder of the Verilog program
rs_decoder_31_19_6_latest.tar.
- RS解码器的FPGA实现，有TestBench,RS decoder FPGA to achieve, there TestBench
final_decode
- rs解码器在fpga上的实现，采用的modelsim开发平台 -rs on fpga decoder in the realization of the development platform used in modelsim
rs_encorder
- RS编码的fpga实现，详细的vhdl文档，可以硬件实现。-RS coding fpga implementation, detailed documentation of vhdl can be implemented by hardware.
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
uarts
- RS-232 interface example for FPGA/EDA developers
rs-codec(255-223)
- RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。-RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.
rscode
- RS编码器在fpga上的实现，用的modelsim开发环境-RS encoder in the realization of the fpga, development environment used in modelsim
rs_encoder
- RS编码器的fpga实现，有TESTBench-RS encoder to achieve the fpga, and TESTBench
rs_5_3_gf256_latest.tar
- this paper deal with rs decoder algorithm-this paper deal with rs decoder algorithm
RS
- 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
rs-232vhdl
- it is the code for doing interfacing between computer and fpga board through rs-232.
RS-design-on-FPGA
- RS算法设计在fpga上的实现文章，很详细-RS design on fpga pdf
RS-encode_FPGA
- 利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤-rs code in FPGA
RS-232CUART
- 主要是利用FPGA进行串口的通信 其中利用到FPGA的开发软件QUARTUS -verilog NIOS UART
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
rs_code
- FPGA实现了RS（255，239）的编译码模块(FPGA implements the RS (255239) encoding and decoding module)
RS
- 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS