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Verilog-HDL
- 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples w
SCM_Data_Acquisition
- 这篇实验报告是关于单片机多路数据采集的，本实验由2大部分组成：1、为用EPOROM构成的心电信号发生器；2、为多路信号的微机采集与显示；第一部分实验主要研究可编程序存储器EPROM的非计算机应用。把存储在EPROM中的数字心电信号读出并通过D/A转换为模拟信号显示在示波器屏幕上。 第二部分实验的目的是研究一个数据采集系统，该系统利用ECD-51型单片机为中心，由D/A芯片等将各种低频信号以及由EPROM产生的模拟人体心电信号变换成离散的数字信号存入微机内存，以待进行数据处理和分析，然后再通过
DTMF_tone_generation_and_detection
- This application report describes the implementation of a dual-tone multiple frequency (DTMF) tone generator and detector. The author provides some theoretical background on the algorithms used for tone generation and detection, and documents the a
boxingfasheng
- 用汇编语言编写的波形发生器，是课程设计，可以运行，包括完整的报告-Written in assembly language waveform generator, is the course design, you can run, including the full report
sine-wave-generator
- 正弦波课程设计报告...含文档和程序代码-Sine wave course design report containing documentation and program code ...
6040404
- Signal generator final report
EWB_eclock
- 用方波信号发生器发出1HZ的稳定的方波信号作为CP信号输入 ,秒计数器满60向分计数器进位,分计数器满60向小时进位,小时计数器按“23翻0”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒。并具有可整点报时与定时闹钟的功能。 本数字钟的功能列表如下： 1）基本功能：秒、分钟、小时计时、显示及校对； 2）整点报时功能：在每小时59分50秒开始500Hz频率发声提示，整点时1000Hz发声，之后声音停止； 3）定时报闹功能：可设定闹钟定点报闹，可用开
VHDL-music-generator-report-code
- VHDL实现音乐发生器,并进行FPGA验证！报告中含有各模块详细代码，和仿真波形！-VHDL music generator and FPGA verification! The report contains a detailed code of each module, and the simulation waveform!
Signal-Generator
- STC89C52控制DDS信号发生器程序 Keil uVision3；AD9850方波正弦波信号发生，频率，幅度可步进调节，详见设计报告（03年电子设计大赛题目）-STC89C52 control DDS signal generator Keil uVision3 AD9850 square wave sine wave signal generator, frequency, amplitude can step adjustment, as detailed design report
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
Random-number-generator-verilog
- Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
xinhaofashen
- 信号发生器的报告，包含电路连接图和代码以及解释-Signal generator report, including circuit connection diagram and code and interpretation
e12HDB3
- 清华大学电子工程系 HDB3实验报告 包括：M序列发生器，编码器，解码器-Electronic Engineering, Tsinghua University HDB3 lab report include: M sequence generator, encoders, decoders
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of