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utx
- UTOPIA L2接口发送VERILOG代码-UTOPIA L2 interfaces sent VERILOG code
UTOPIA
- utopia接口模块VHDL源码,实现UTOPIA接口功能,可进行UTOPIA接口仿真-utopia interface module VHDL source code to achieve UTOPIA interface functions can be carried out UTOPIA Interface Simulation
TranslateToUTOPIA
- VHDL写一个转换到utopia接口的转换源程序.可以进行utopia接口的仿真试验-VHDL to write a converter to convert source utopia interface. Can utopia interface simulation test
utopia
- utopia，system verilog写的CPU测试平台代码-utopia, system verilog code written in CPU test platform
6455Utopia2_example
- C语言编写的DSP例程,是一个Utopia程序 希望对初学者有用-The DSP routines written in C, a Utopia procedures hope useful for beginners