搜索资源列表
100vhdl
- 100个VHDL的程序实例集 加法器 比较器 分频等-100 instances of VHDL procedures set of adder comparator frequency, etc.
mux4
- 基于VHDL的四位加法器的实现,通过此加法器的设计,可以扩展到更多位的加法器的设计-VHDL-based implementation of the four adder, through the design of this adder, can be extended to more bits Adder
chap3_adder
- FPGA学习资料-VHDL语言实现的加法器-FPGA implementation of learning materials-VHDL Adder
adder_vhdl
- 经典的加法器程序,用VHDL写的,包括测试向量-Classical adder program, written using VHDL, including test vectors
alu
- 加法器源码 CPU设计专用 VHDL实现-Source adder VHDL CPU designed to achieve specific
cla16
- 16位超前进位加法器的源代码,整个工程文件都有,是在ISE10.1下建立的,可以帮助理解超前进位原理(对了,是Verilog的,因为上面没看到只好选VHDL了)-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
add8(2)
- 一个基于VHDL语言的8位加法器,有进位功能。-A language based on VHDL 8-bit adder, a carry function.
ADDER
- 基于vhdl硬件描述语言设计的加法器电路 -Hardware descr iption language design based on vhdl adder circuit
add32
- 32位加法器,基于vhdl语言,主要用于测试算法-32-bit adder, based on the vhdl language, mainly used for testing algorithms
baweijiafaqi
- 八位加法器的VHDL程序,可以实现八位二进制数的相加。-Eight adder VHDL program that can achieve the sum of eight binary digits.
100vhdl
- VHDL100个例子,讲述VHDL基本应用,如加法器,移位寄存器等。-VHDL100 example, about VHDL basic applications, such as adders, shift registers.
Adder
- VHDL语言设计的加法器,在试验箱上使用8个拨码开关设置要加的2个数,按键按下输出相加的结果,在试验箱上测试通过。-Adder VHDL language design, in the chamber using the DIP switch setting 8 to 2 to add the number of keys pressed result of the addition output of the chamber on the test.
summator
- 加法器是产生数的和的装置。常用作计算机算术逻辑部件,执行逻辑操作、移位与指令调用。在电子学中,加法器是一种数位电路,其可进行数字的加法计算。在现代的电脑中,加法器存在于算术逻辑单元之中。 加法器可以用来表示各种数值,如:BCD、加三码,主要的加法器是以二进制作运算。加法器可以用组合逻辑电路实现也可以用VHDL语言实现。-Adder is generated and the number of devices. Arithmetic logic unit is used as a computer
bcdfa
- 计算机组成原理,4位加法器实验VHDL代码。已运行成功。-Computer organization, 4-bit adder VHDL code experiments. Has been running successfully.
adder
- 较好的加法器VHDL代码,大家需要可以下载,谢谢。-Better adder VHDL code, we need to download, thank you.
add
- 加法器的实现,用VHDL/FPGA/Verilog制作的实现的- adding machine use VHDL/FPGA/Verilog
yibanjiafaqidesheji-EDA
- 基于FPGA的快速加法器的设计与实现,在VHDL环境中波形图显示出结果,可以用二进制,十进制,十六进制表示 -FPGA-based fast adder design and implementation in VHDL environment, the results in the waveform display, you can use binary, decimal, hexadecimal
butterfly1
- FFT 蝶形处理器的VHDL代码,由一个加法器,一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
FPGA
- sin函数 交通灯 加法器的vhdl代码 自写,参考-sin function
mult
- 4级流水乘法器,本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计,编写VHDL程序完成了乘法器的功能设计,并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete