搜索资源列表
VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
ARM32ALU
- VHDL ARM 32位ALU的设计，基于Quaryus II平台-VHDL ARM 32 位 ALU design platform based on Quaryus II
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
ARMAndFPGAAppliingOnDataCommunicatin
- ARM处理器和FPGA在数据传输中的应用与研究-ARM processor and FPGA data transmission in the Application and Research
ARM7_verilog
- arm 7 verilog code used setup soc
test
- wARM体系结构的VHDL设计，研究ARM体系设计很有用-WARM VHDL architecture design, research useful ARM System Design
arm
- ARM教程,理解精辟，言简意赅，不错哦，欢迎大家-arm language
ARMCore_Rev12
- arm 7 core manual is good reference.
ARMCORE
- mcu arm ,easy study and understand,for arm energer,it s very good.
apb_bridge
- arm ambm 2.0 primecell算法 ahb 与 apb通讯的转换模块-arm ambm 2.0 primecell algorithm ahb conversion and communications module apb
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
uart
- 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
AMBA_V2.0_CN
- ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
core_arm
- 从opencore找都的ARM的IP CORE。有详细说明。-From opencore to find all of the ARM' s IP CORE. Is described in detail.
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
12130_ARM_Core
- arm 核，VHDL语言描述的IP软核，仅供学习-arm-core, VHDL language to describe the IP soft core, only to learn
spi-vhdl
- 用vhdl写的spi通信，arm为主设备，fpga为从设备，其中包括代码，以及具体协议-failed to translate