搜索资源列表
1076 IEEE Standard VHDL Language Reference Manual.
- 1076-2002 IEEE Standard VHDL Language Reference Manual-1076-2002 IEEE Standard VHDL Language Ref validated Manual
用vhdl语言编写的2进制到10进制转换的程序
- 本文为用vhdl语言编写的2进制到10进制转换的程序，为doc格式，使用前复制于maxplus等相应软件中使用。,This article was prepared by using VHDL language 2 hex to 10 hex conversion procedures for the doc format, the use of pre-replication in maxplus, such as the use of corresponding software.
tlc549.数字电压表的VHDL语言实现
- 数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程,The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD
DPLL(VHDL).rar
- 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开,The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
motorcontrol(vhdl).rar
- 基于FPGA的直电机伺服系统的设计的代码，VHDL语言。包括前馈控制，AD1674控制模块，ADC0809控制模块，前馈控制模块，分频模块等。,FPGA-based servo system direct the design of the electrical code, VHDL language. Including feed-forward control, AD1674 control module, ADC0809 control module, feed-forward contr
VHDL
- 基于vhdl语言的音乐播放器的设计代码。请各位可以根据自己的需要用。-Vhdl language-based music player, the design of the code. Members can be used according to their own needs.
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
I2C_Interface(VHDL)
- I2C总线接口FPGA的实现代码，全部为VHDL语言源码文件，内附设计实用说明文档。-I2C bus interface FPGA implementation of the code, all source files for the VHDL language, included the design and practical documentation.
vhdl
- vhdl语言例程集锦.pdf，全部的例子，看你会不会偷了-VHDL language routines Collection. pdf, all the examples, you will not see stealing
VHDL-Handbook
- Vhdl hand book a very good reference for vhdl language describing , syntax of the language with examples to each syntax are explained in details in the book.-Vhdl hand book a very good reference for vhdl language describing , syntax of the language
VHDL
- DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
vhdl
- VHDL语言例程集锦,语言:英文 内容<<Examples of VHDL Descr iptions>> <<-VHDL Language Guide,language: English
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
vhdl
- 学习vhdl语言的实用教程，很详细，从零开始学起，简单易行，支持-Vhdl language learning and practical tutorial is very detailed, from scratch to learn, easy to support
vhdl-2008-just-the-new-stuff-systems-on-silicon.r
- VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL
1076_ieee_standard_vhdl_language_reference_manual.
- 1076 ieee standard vhdl language reference manual-1076 ieee standard vhdl language reference manual.pdf
h
- huffman编码的vhdl语言实现 课程设计做的 有点用的-huffman coding vhdl language curriculum design to achieve a little bit to do with the
VHDL
- 由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and
VHDL
- （1）用VHDL语言编写程序，在EDA实验板上实现 （2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。 （3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。 用VHDL语言编写程序，在EDA实验板上实现 （4） 整点报时。 （5）. 闹钟功能。 （6）．秒表功能。-(1) using VHDL language program, in the EDA
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.