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64位乘法器verilog
- 64位乘法器的源码，测试代码以及详细的报告
verilog32位浮点数乘法器
- 采用verilog写的32位浮点数乘法器，组合电路，只需要一个时钟周期就可完成运算
verilog乘法器设计
- verilog乘法器设计
add.rar
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）,Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
MULT
- 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
multi16
- verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
pipe_mul8
- verilog实现的流水线8位乘法器，效率高，代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
常用乘法器设计
- 采用Verilog语言设计的几种常用乘法器。(several multiplier designed by verilog)
mul8
- 用verilog设计了一个两个8位二进制数的乘法器(A multiplier of two 8 bit binary numbers is designed with Verilog)
有符号小数乘法器
- 改进的verilog乘法器，改进了此项乘法，更利于在硬件中的使用(introduce this funcation in this code.)
GF乘法器
- 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
64位乘法器
- 基于fpga的64位乘法器的实现，基于Verilog(Implementation of 64-bit multiplier based on FPGA)
multiplication
- 在FPGA里面实现了多位乘法器的功能，并用modelsim进行了仿真，还对该乘法器进行了优化(The function of multi-bit multiplier is realized in the FPGA, and it is simulated with modelsim, and the multiplier is optimized)
multi
- 基于Verilog HDL 的乘法器，可以实现一些功能的计算(Multiplier based on Verilog HDL)