搜索资源列表
B3LabGuide
- xilinx 的FPGA开发板的相关资料，可以很好地熟悉掌握开发板的使用，加快开发进度-Xilinx FPGA development board information, is a good way to master the use of the development board, speed up the development pro
basys3_rm
- xilinx 的FPGA开发板的相关资料，可以很好地熟悉掌握开发板的使用，加快开发进度-Xilinx FPGA development board information, is a good way to master the use of the development board, speed up the development pro
basys3_sch
- xilinx的FPGA开发板的相关资料，可以很好地熟悉掌握开发板的使用，加快开发进度-Xilinx FPGA development board information, is a good way to master the use of the development board, speed up the development progress
Xilinx_I2C
- Xilinx FPGA的I2C Master例子-Xilinx examples of I2C Master
USB_SoftLock
- USB SoftLock, 包含VHDL for Xilinx FPGA，上位机驱动以及应用程序-USB SoftLock, Include VHDL for Xilinx FPGA, PC Driver and App
LCD-IP-CORE
- LCD Controller IP for Xilinx FPGA
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
testadcom
- XILINX FPGA模拟量采样通信测试 XC6SLX9完成AD采样通过光纤通信上传给XILINX XC6SLX25。-XILINX FPGA XC6SLX9 XC6SLX25
SHORT_TRAINING
- 基于XILINX FPGA的OFDM通信系统基带设计之短训练序列模块源码-Baseband OFDM communication system design based on XILINX FPGA module source of short training sequence
Xilinx-7
- Xilinx 7系列的FPGA资料，初学者必看-Xilinx 7 series FPGA data, beginners must see
reconf. router code xylinx
- design and fpga implementation of Routing algorithm for NOC
xc3sprog_rev780_working_with_xc6slx9_spi
- xc3sprog working version see http://xc3sprog.sourceforge.net/ use with https://sourceforge.net/projects/libusb-win32/
04_led_test
- verilog 入门 流水灯verilog 入门 verilog 入门 verilog 入门(verilog led test xilinx)
05_key_test
- fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)
07_uart_test
- fpga 串口 Verilog 黑金的板子，入门(fpga uart test xilinx)
XilinxVirtualCable-master
- Xilinx虚拟连接，这是一种基于TCP/IP协议的通信技术，以实现JTAG功能，通过这样的连接，可以访问开发的FPGA或者SOC，而不需要通过传统的JTAG电缆。(Xilinx Virtual Cable (XVC) is a TCP/IP-based communication protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design wi
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
FPGA_program
- 采用verilog实现RTLAB多路驱动程序(Using Verilog to achieve RTLAB multi-channel driver)
Vivado 2016.1 安装流程
- Vivado是 Xilinx新一代针对7系列及后续 系列及后续 FPGA 的开发平台。 Vivado 2016.1是官方首个支持 是官方首个支持 win10的版本。(Vivado is the new generation of Xilinx for the 7 and subsequent series and subsequent FPGA development platform. Vivado 2016.1 is the official first support, is the of
xapp585
- LVDS并行数据传输，来自XILINX官网(LVDS Parallel Data Transfer)