搜索资源列表
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
adc2
- ADC control in VHDL language. Spartan 3E starter pack ISE 10.1
16bitADC
- verilog实现的16位模数转换器参考源代码-verilog to achieve 16-bit ADC reference source code
adc
- 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
ADC-
- it is the document & source code in verilog of adc using sparten 3e fpga kit
adc
- VERILOG编程，利用状态机实现对TLC549的采样控制，实验时可调节电位器RW1（在开发板底板左下角），改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。 -Implementation of sampling control of TLC549 using state machine, adjustable potentiometer RW1 experiment (in the development board bottom left corner), change t
tugedafinal
- 使用Verilog HDL语言写的关于实现对ADC、MDC控制的程序，个人使用Quartus 7.2,在上面进行过仿真，暂时还没有发现问题-Using Verilog HDL language written on the realization of the ADC, MDC control procedures, personal use Quartus 7.2, in the above simulation carried out have had no problems found
adc
- 使用verilog 硬件描述语言编写的ad采样模块，希望对大家有用。(Using Verilog hardware descr iption language written in AD sampling module, I hope useful for everyone)