对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.

基于STM32F103实现AES算法的工程，支持128,196,256位AES(Based on STM32F103, AES algorithm is implemented, supporting 128196256 bit AES.)