搜索资源列表
des-verilog
- des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Viterbi_v
- Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
verilog-som
- 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
magnitude
- Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algori
sha-1.rar
- 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
CORDIC_ATAN.rar
- 使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代,Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations
FIRde-verilog-shixian
- 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
1024FFT-verilog-hdl
- 基于spartan 3e 的IFFT算法verilog HDL程序-Based on the verilog 3e Spartan IFFT algorithm of HDL program
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Verilog
- 基于Verilog的编码用BOOTH算法和移位相加实现乘法运算-BOOTH Algorithm with multiplication
ccmul
- FFT旋转因子，旋转因子是蝶形运算的组成部分，是数字信号处理FFT算法的基础部分-FFT twiddle factor, rotation factor is an integral part of the butterfly, digital signal processing is a fundamental part of FFT algorithm
4x4_bits_Booth_Algorithm
- Verilog写的booth算法，是微机原理的基本算法，对Verilog的入门有帮助，包含代码和报告-Booth algorithm written in Verilog is the basic principle of computer algorithms, Verilog entry helpful, the report contains the code and
factorial
- verilog code for factorial algorithm
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
fir_lms
- finite impulse response LMS algorithm verilog code
FPGA-DDS-algorithm
- 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
new rsa algorithm
- this is a very good algorithm to download
VLSI verilog
- booth multiplier using booth algorithm