搜索资源列表
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
async_fifo
- async_fifo，与VHDL相关，硬件开发相关，FPGA相关，够了-async_fifo, and VHDL-related, hardware related to the development, FPGA related enough
async_fifo
- 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
async_fifo
- 用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。（不能直接使用。）-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)