verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.

信噪比可变的加性高斯白噪声信道下信号发生器的VHDL语言编程实现-the realization of data-creater on AWGN channel

高斯白噪声的VHDL实现。伪随机序列只能输出均匀噪声，需要打乱相关性。-awgn in vhdl