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vhdlsample
- vhdl program for bcd conter to 7 segment display
eg
- 众多的小源程序 很实用如BCD译码数码管显示-Very useful source of many of the small digital display, such as BCD decoding
BCDMULTIPLIER
- BCD MULTIPLIER PROGRAM
count
- 设置一位控制位M，要求M=0：模23计数；M=1：模109计数；计数结果用两位静态数码管显示，显示BCD码； -Setting a control bit M, requires M = 0: mode 23 counts M = 1: model 109 counts counting results with the two of static digital display to show BCD code
adder2
- 此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。-This source code is based on the Verilog language def
2
- 将一个字节BCD码转换为两个ASCII码 例如10H变成30H和31H 结果放在缓冲区中-BCD code to convert a byte into two ASCII codes such as 30H and 31H 10H into results on the buffer
division_imp4_v5
- Code VHDL for Newton Raphson BCD Division and Carry Save Multiplication in BCD
Sum_Rest_BCD
- VHDL Sum and Rest BCD
f
- 一个BCD的优先编码器电路，输入为10个开关的状态，要求输出开 关对应的编码。输出编码用4位表示，第一个开关为0时，输出为0000时，第二个开关为0时，输出为0001时，...... 第10个开关为0时，输出为1001。第10个开关的优先级最高。当没有按键按下时，输出信号E为1。有按键按下时，输出信号E为0。 -A BCD priority encoder circuit, the input switches for the 10 state code requirements of
verilog_decimal_BCD
- 用verilog写的十进制转BCD码,希望对大家有帮助-Verilog to write with decimal switch BCD, we hope to help
m41t11_RTC
- The M41T11is a low-power serial real time clock with 56 bytes of NVRAM. A built-in 32.768 kHz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used for the clock/calendar function and are configured in binary coded
Advanced_Adders
- Advanced topic on adders including: Carry Look Ahead Adder, Binary Parallel Adder/Subtractor, BCD adder circuit, Binary mutiplier circuit.
bcd2bin
- 用Verilog实现二进制码转变为bcd码-binary change into bcd code using verilog language
bcd_led_printer
- 单片机硬件译码--BCD数码管 附 protuces 仿真电路图 汇编程序代码-Microcontroller hardware decoding- BCD digital circuit simulation with protuces assembler code
BCDEncoder8421BCD
- BCD编码器的设计(8421BCD)，一个很实用的模块-BCD Encoder (8421BCD), a very practical module
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
bin_BCD
- conversor BCD-7SEGMENTOS
23
- 16进制转BCD代码源代码51单片机亲测好用，放心copy-BCD code of 16 hex turn pro test source code 51 SCM easy to use, rest assured copy
03-jk-ff-BCDcounter
- JK-flip flup-BCD counter with proteus
SCM_in_BCD_conversion
- 单片机中BCD码的转换 涉及十进制与BCD的相互转换 及十六进制与BCD的相互转换-SCM in conversion of BCD involving decimal and BCD mutual transformation and hex and BCD conversion to each other