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cache utility
- cache测试软件，通过该小程序可以了解一些有关cache工作原理．-a program to test cache,with the progran some theory of the cache can be realized.
ARM-program
- ARM体系结构和编程,介绍ARM CPU 的细节，包括结构，寻址，指令集，汇编语言，cache管理，存储，函数调用参数传递，交叉编译连接及调试。-ARM architecture and programming on the ARM CPU details, including the structure, addressing, instruction set, assembly language, cache management, storage, transfer function ca
Vc实现的cache模拟
- 计算机体系结构中cache实现原理及解决方案的模拟程序.-Computer Architecture cache Principle and solutions simulation program.
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
LED_Test(s3c2440)
- 这是学ARM9和RealView MDK的一个很好的例程，这个例程简单易懂。这个例程可以用开发板是的LED灯和仿真器来测试硬件的好坏，还可以CACHE对程序运行速度的影响，测试设置FCLK的频率。-This is the ARM9 and RealView MDK learn a good routine, the routine is easy to understand. This routine can use the development board is the LED lights
DHRY
- The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-performance benchmark test originally developed by Reinhold Weicker in 1984. This benchmark is used to measure and compare the performance of different
VSProjects
- 基于ArcGIS Server的Mobile程序，可以从服务器端下载地图并生成Cache文件。-This is a ArcGIS Mobile Program.
CACHE
- 一个arm7开发板上cathe内存测试程序，该程序用c语言编写。-a arm7 Development Board cathe memory test program, the program is available c language.
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
ram32
- 并行RAM程序，2位并行读取，可以参考用于要求高速缓存的设计。-Parallel RAM program, two parallel reading, you can refer to the cache for the required design.
ARM-System-Developers-Guide..
- 本书从软件设计的角度，全面、系统地介绍了arm处理器的基本体系结构和软件设计与优化方法。内容包括：arm处理器基础；arm/thumb指令集；c语言与汇编语言程序的设计与优化；基本运算、操作的优化；基于arm的dsp；异常与中断处理；固件与嵌入式os；cache与存储器管理；armv6体系结构的特点等。全书内容完整，针对各种不同的arm内核系统结构都有详尽论述，并有大量的例子和源代码。附录给出了完整的armv4/v5/thumb指令的功能、编码、周期定时以及汇编参考。 -This book
3.2.2-DEC5502_CACHE
- 这是我们学校的DSP实验箱5502的cache实验程序,保证可以用,功能很全,程序中有对DSP初始化,CACHE初始化,然后读写SDRAM.-This is our school s DSP 5502 kit s cache test procedures to ensure that you can use, features a very full, the program in the DSP initialization, CACHE initialization, and then w
Virtex-5-FPGA-Data-Sheet
- 本程序基于xilinx fpga，v5，verilog语言，主要用于数据采集，采集频率可达500m，通过pingpang缓存进行数据转发。-The program xilinx fpga, v5, verilog language, mainly used for data acquisition, acquisition frequency of up to 500m, through data forwarding pingpang cache.
ppt
- linux系统编程，计算机系统的基本构成 处理器，主存，I/O模块，系统总线 中断的分类 程序中断，时钟中断，I/O中断，硬件失效中断 存储器的层次结构 Register->cache->main memory->disk 操作模式分为？内核模式，用户模式任何资源分配和调度策略都必须考虑的三个因素公平性，有差别的响应，有效性-linux system programming, the basic structure of a computer syste
run time expandable cache
- Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In t
stm32-iap-small-data
- 1.此代码基于红牛开发板，请根据自己的板子进行修改。 2.通过修改网上的代码实现，修改前的功能开了一个很大的缓存接收app数据，然后一次性全部数据写入， 但是这个在实际应用中没多大用，所以修改为一次写入128个字节。 3.程序flash的偏移地址为0x8010000，所以app编译前应该在mdk中设置 Option窗口->Target页->IROM1,start 改为 0x8010000 4.设置中断向量重映射，我用的方法是在app端的main函
CCD-data
- 单片机作为主控，对CCD的数据进行采集、缓存（FIFO）、传输（RS485）的程序。单片机为C8051F5-MCU as the master of CCD data acquisition, cache (FIFO), transmission (RS485) program. C8051F500 microcontroller
tlkcsharp
- 一个公司的设备采集项目用到的数据实时采集终端程序 可以动态监控多个模拟量、开关量及485接口传递的数据，支持本机数据缓存，支持实时远程传递数据，支持实时动态图表显示数据状态-Real-time collection project a company s equipment used in data collection terminal program You can dynamically monitor multiple analog, digital, and 485 trans
BSP_USART1
- STM32串口程序，中断发送接收，128字节缓存，很好用，很实用-STM32 serial program, the interrupt to send and receive, 128 bytes cache, useful, very practical