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32bitcpu
- 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations righ
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
waveform
- Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形-Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform
verilog
- 波形发生器，产生4种波形，能够自己手动转换，并能调节输出频率-Waveform generator to produce four kinds of waveforms that can convert your manual, and can adjust the output frequency
waveform_-generator
- 简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。-imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL.
OFDM_retiming
- 基于Verilog的OFDM时钟恢复模块，在做全数字OFDM的时候是关键模块，可以在FPGA上实现。-Verilog-OFDM-based clock recovery module, doing all-digital OFDM time is the key module can be implemented on the FPGA.
f_meter
- Verilog频率计,可以测出1~9999hz的频率，分模块做成顶层文件-Verilog frequency meter can measure 1 ~ 9999hz frequency, sub-module is made of top-level files
PWM
- 调制输出的脉冲宽度，进行电机的控制，能，控制电机的速度，能正负反转！-Pulse width modulated output, the motor control, can control the motor speed, can reverse the positive and negative!
USB
- USB控制器的VERILOG工程文件，工程为ISE的，可以编译通过，压箱底的东西了-USB controller VERILOG project file, works for the ISE, you can compile, pressure bottom of things
tft_lcd
- 用verilog写的TFT液晶驱动程序，本程序经下载到开饭板后，能正常运行-Verilog write with TFT LCD driver, this program downloaded to the have dinner plate, can normal operation
DDS
- 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
div_frequency
- 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
sdModel
- SD Card的verilog模拟模型，可以配合开发SD Controller使用-SD Card the verilog simulation model can be used with the development of SD Controller
Verilog----m
- verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
1day11-keyboard
- 清华大学电子课程设计：Verilog语言编写，可在QuartusII完全正确运行，FPGA下载，键盘按键输出相对应数字，有防抖功能-Verilog language, can be run in QuartusII entirely correct, FPGA download, keyboard keys corresponding to the output figures, anti-shake function
verilog
- 都是介绍VHDL的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
DE2-VGA-LED
- verilog HDL 语言编写的，FPGA的数码管和VGA的显示。调用时不必修改源码，只需引脚映射对就可以-verilog HDL language, FPGA digital and VGA display. Call without having to modify source code, you can just pin on the map
Verilog
- 这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。-This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.
can_latest.tar
- 用Verilog写的CAN协议IP核 已经验证可以使用 -CAN protocol written in Verilog IP core has been verified using