搜索资源列表
uart
- 实现串口发送和接收功能,数据处理模块可自行修改。(Serial port to send and receive functions, data processing module can modify its own.)
float_2_int.v
- 最全的,最简单,32位浮点数转整数,32位整数转浮点数,直接可以移植,已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
can_loopback_test
- 实现了can控制器Verilog编程使用niosII 开发平台(Can controller Verilog programming, the use of niosII development platform)
avalon-i2c
- 基于verilog的I2C实现,可以通过软核或者ARM核进行控制哦。(The implementation of I2C based on Verilog can be controlled by soft core or ARM core)
Xilinx新一代FPGA设计套件Vivado配套资料
- verilog经典教程,入门者的必选书籍,非常实用,可以学习到很多的知识(verilog classic tutorial, entry must be books, very practical, you can learn a lot of knowledge)
Verilog_HDL时序篇 教程及代码
- 对于verilog时序篇较好的一套学习资料,附有源代码及工程文件,可跟着教程自学(A good set of learning information for Verilog timing chapter, with source code and engineering documents, you can follow the tutorial self-study)
de2_build
- De2_build: It contains the FPGA configuration file of the comprehensive Nios II system in Section 16.10.2 and software image files for the DE2 board. These files can be used for quick demo or software development. Note that the files can only be us
source code
- 2.6'TFT_LCD驱动源程序,可以在quartusII平台上直接运行(2.6'TFT_LCD driver source program, you can run directly on the quartus II platform)
jingxiang_beipin
- 实现编码器鉴向和4倍频,可用于电机测速等。(To achieve encoder and 4 times the frequency, can be used for motor speed and so on.)
ve_lab
- verilog语言实现智能交通灯控制系统,除现有交通灯系统基本功能以外,还包括未来交通可能出现的一些需要智能控制的情况进行自定义规则(比如检测车流量来控制交通灯持续时间,高峰期主干道绿灯时间将加倍等规则)(The project was completed by myself about two months ago. I think it will be useful for traffic control system.But there are many points needed to
uart_test
- 通过FPGA,实现串口传输数据,并且可以支持多种不同的波特率,用EP4CE22F17芯片实现。(Through the FPGA, serial transmission data, and can support a variety of baud rates, using EP4CE22F17 chip implementation.)
vga_7_0728
- 用vga显示数字钟,通过串口可以控制时间显示(With vga digital clock, through the serial port can control the time display)
display_1
- veilog程序可以在fpga上完成数字钟程序(Verilog program can be completed on the digital clock fpga procedures)
5 +3
- FPGA发送SOS呼救,按键可以发送信号,复位停止发送(FPGA sends SOS to save, key can send signal, reset to stop sending)
clock
- 自己开发的电子时钟小程序,通过数码管显示时间,key1和key2控制校时校分,key3切换时钟模式和闹钟模式,切换到闹钟模式再按key1和key2即可设定闹钟时间。key4控制开启/关闭闹钟。有整点报时功能。(Self developed electronic clock applet, through the digital tube display time, key1 and key2 control time correction, Key3 switch clock mode and
Xilinx的增量编译技术
- 增量编译技术,其基本原理就是根据前一次编译的结果,只重新编译部分修改过设计,其它部分则沿用前一次编译的结果,这样就可以缩短总体的编译时间(Incremental compilation technology, the basic principle is based on the results of the previous compilation, only re-editing part of the modified design, the other part is based on
ADC_Data_Recv_Module
- 接收机测试输入信号, 生成正余弦波,采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
Verilog_1Gb_DDR3_G_Die
- ddr3控制器,速率可达1Gbps,语言使用verilog,已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
Module基础全集
- 如题,各种veirlog 基础代码大全,虽功能不及ip核,但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
帧同步
- 这是一个可以实现帧同步的编码,应用verilog编码(This is a coding that can implement frame synchronization, using Verilog coding)