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complete
- 基于Verilog写的测信号频率和幅度得程序,可用-Written in Verilog-based test signal frequency and amplitude were procedures, can be used
calculator
- 课设一个,又臭又长,是一个用verilog编写的计算器,对应革新科技的某个sopc开发平台,键盘会扫描,七段二极管会译码且是并行输出,上传的是整个工程,在该开发平台上基本正常,主程序段编写的较为幼稚,希望大家多多扔玉。注:主程序段预计做八位计算器,后来因为实验平台只有六个数码管无奈之下后两位没接,主程序中的ac有问题,在开发平台上没效果,压缩包里的图是主程序在quartus下的仿真图,开发环境是quartus,不知应选哪项。最后:初次上传欢迎指正 -Set up a class, but als
sdr_verilog
- 用Verilog实现SDR_SDRAM的控制器,可用FPGA实现对普通SDRAM的读写操作!-SDR_SDRAM using Verilog implementation of the controller, the FPGA can be used to achieve the ordinary SDRAM read and write operations!
BIN_CV_MEN
- 可將2進位檔案 轉換成適合verilog應用的文字檔-2 into digital files can be converted to a text file for verilog applications
ALUALUcontrol
- 实现32位的ALU,使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写,实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
fir_memory
- 用memory编写的verilog代码,可用于工程应用,已经过仿真-Verilog code written with the memory can be used for engineering applications, has been simulation
example
- 自己编写的经过QuartusII验证的Verilog HDL程序,可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features
Chapter-8
- Verilog编写的CAN通讯程序,通过验证,并支持CAN1.1,CAN2.0b协议。-CAN communication procedures written in Verilog, through validation, and support CAN1.1, CAN2.0b agreement.
uart_nbit
- 用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the progr
Altera_Verilog_Coding_Style_Proposal_final
- Altera的Verilog 代码规范,讲解的还可以-Altera' s Verilog code specifications, explanations can also be
RISCCPU
- 简单的CPU设计流程PPT,用于教学目的,可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
LCD1602_Driver
- 自己课设上写的基于Verilog的LCD1602驱动器,能自定义字符,16x2显示位均已引出,可以用于纯硬件的电子钟等显示-To write their own lessons based on the LCD1602-based Verilog driver can customize the character, 16x2 display spaces have led to, can be used for pure hardware such as an electronic clock
an294_16x16
- Verilog编写的16x16的可交叉的CPLD程序,可用在16个VGA入,16个VGA输出-16x16 cross switch CPLD software wrote by verilog which can be used in 16 VGA input , 16 VGA output application
ntc
- NTC电阻在VERILOG HDL中的曲线表,使用1MA恒流源供电,用AD对其采集电压,并以12BIT形式输出查表即可达到实际温度值,本表占用450个12位存储单元-NTC resistor VERILOG HDL in the curve of the table, use the 1MA current source power supply voltages were collected with AD and in the form of the output look-up table
method
- i need to refer and search for calculator verilog.hope i can find answer from it.
PS2andRS232
- 基于Verilog语言PS2接口和RS232接口的实现 有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
AUTO_START
- verilog 编写的代码 方便使用 能自启动的七进制计数器-verilog code written in easy to use can be self-starting of the seven binary counter
DDSVerilog
- Verilog 实现的DDS源码,可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
Verilogalotofexamples
- 关于VERilog 很多的例程,虽然不能处理比较大的应用,但是对于中小型的应用还是不错的-About VERilog lot of routines, although it can not handle larger applications, but applications for small and medium or good
digital_frequency
- 用verilog实现数字频率计的设计,具有自动换挡功能,采用t法和m法设计,低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.