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paomadeng
- 用verilog语言实现跑马灯功能，编译已通过，可以成功在实验箱上运行-Marquee with verilog language function, the compiler has passed, you can successfully run on the test box
ADSP2011Local
- pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at r
led
- verilog的程序，调试按键以及led显示内容，编写灵活简单，可以借鉴-verilog program, debug button and led display, write simple and flexible, you can learn from
task2
- Verilog语言，可在QuartusII正确运行，实现远程控制系统，利用异步串行通信，PC发送数据FPGA接收，实现本地回环模式。-清华大学电子课程设计：Verilog language, you can QuartusII correctly, remote control systems, using asynchronous serial communication, PC to send data received FPGA to achieve the local loopback
task22constant
- 清华大学电子课程设计：Verilog语言，Quartus可以正确运行，下载到FPGA上可完成PC与FPGA一串数据的连续收发，且实现本地回环，异步串口通信-Verilog language, Quartus can be correctly downloaded to the FPGA to be completed by PC and FPGA transceivers continuous string of data, and implement local loop, asynchron
calculator_final
- 清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大-Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
signal
- EP2C5Q208C8 verilog 产生m序列 50M晶振分频得到时钟，可以选择10种时钟- -！-EP2C5Q208C8 verilog 50M m-sequences generated by dividing the crystal clock, you can choose from 10 clock--!
I2C
- I2C的verilog实现，通过验证可以使用，需要的可以下载-The I2C verilog implementation, validation can be used, need can be downloaded
my_FIFO
- FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
my_VGA
- FPGA驱动VGA显示，通过验证，需要的可以下载。verilog实现-VGA display driven by the FPGA, through validation, need can be downloaded. verilog implementation
count4
- 四位加法器的Verilog实现，可以实现综合工具对其综合-Four adder Verilog implementation of their comprehensive synthesis tool can
1602lcd
- veriog HDL语言实现LCD1602显示-This program can drive the LCD1602 with verilog HDL language
verilog_xiyiji
- 为Verilog Hdl 代码实现自动洗衣机启动，复位，水洗，排水，脱水，等功能，并能显示洗衣机的工作状态-Code for the Verilog Hdl automatic washing machine start, reset, washing, drainage, dewatering, and other functions, and can display the working status of washing machine
VGA_COLOR_LINES
- 利用Verilog语言写的VGA彩条显示控制电路，显示器模式：1280X1024@60HZ.按下K1，K2键可控制彩条显示的模式-Use Verilog language is written VGA display control circuit, striped display mode: 1280 X1024 @ 60 HZ. Press the K1, K2 key can control the color display mode. Article
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
password
- verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the
odd_div
- 利用Verilog实现奇术次分频，这里只举了一个例子，但任意奇数次分频均可以用该原理实现。-Patients achieving the odd times using Verilog frequency, just to cite one example, but any odd frequency can be achieved with the principle.
test8
- 这是一个Verilog编写的VGA驱动程序，该程序在FPGA开发板上运行后，能在VGA显示上显示一个行走人的动画-This is a VGA driver in Verilog, the program running in the FPGA development board can display a person s walking animation on a VGA display。
Multifunction-digital-clock
- 这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use