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智能计时计数器
- 智能计时计数器 有计两脉冲间隔时间、几脉冲间隔时间、30秒脉冲数等，还有就是根据这些时间做一些运算，51，牵涉到LCD，汇编C混合，计时器的使用。 本人首个正式产品，各位兄弟见笑了。原理图、程序、图片都有。-counter a smart time or two pulse intervals, pulse several time intervals, 30 seconds pulse, and so on. There is, according to the time to do
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirem
微机接口应用设计指导.rar
- 微机原理与接口实验指导，包括：A/D转换实验、 D/A转换实验、255A并行口实验、定时器/计数器、数据排序程序、红绿交通灯实验等等 ,computer interface experiment with the principles of the guide, include : A/D conversion experiments, the D/A conversion experiments, experimental 255A parallel port, timer/counter,
counter.rar
- 初学者学习modelsim的好例子，基于Verilog的计数器，带测试源码，在quartus2运行。,Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
stm32-Frequency-meter
- 使用stm32通用计数器做的一个简易频率计，可以算出脉冲宽度还有其占空比-Done using a general-purpose counter stm32 simple frequency counter, you can calculate the pulse width as well as its duty cycle
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
calendar
- 128*64液晶显示月历模式万年历，proteus仿真电路，计算星期和闰年处理。-128* 64 LCD calendar calendar mode, proteus circuit simulation to calculate a week and leap year deal.
adder4
- 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
CNT10_T
- 这是同步十进制计数器的源程序，有需要的同学可以参照一下！-This is a source synchronous decimal counter, needy students can refer to you!
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
freqm
- a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
counter
- 利用fpga实现秒表。秒表有开始停止，清零的功能-FPGA implementation using a stopwatch. Have begun to stop the stopwatch, Clear function
Counter
- 计数器程式 控制器为AT89c52单片机,设定按钮,加按钮,减按钮：采用共阳七段数码管显示器。*/-Counter AT89c52 program for single-chip controller, set the button, add button, minus button: Yang used a total of Seven-Segment LED display.* /
scorecounter
- yong 89s52 zhizuo de lanqiu jifenpai,yong KEIL he PROTUES da kai.-A basketball score counter sysrem ,use 89s52 as mcu.
VHDL16bitcouner
- 利用VHDL编写的一个简单的16位计数器-VHDL prepared using a simple 16-bit counter
Ripple_Carry_counter
- Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.
TimerCount1
- AVR重要定时计数器1的15种工作模式，包括普通，CTC，快速PWM,相位和频率可调PWM的典型应用-AVR important to counter a 15-time working modes, including normal, CTC, fast PWM, phase and frequency adjustable PWM Typical applications
counter
- 不同频率的两个计数器，第一个计数器向上技术，第二个当第一个计满后向下计数-Two different frequency counter, a counter up the first technical, the second when the first after the expiration of a count down
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal