搜索资源列表
CPLD
- verilog编写的加减6路可逆计数器，用于FPGA对6路脉冲信号的计数-verilog written addition and subtraction 6 way reversible counter for FPGA on the 6-channel pulse count
CPLD-down2
- EPM240 Program,Quartus II 10.0,Verilog
Frequency
- 通过单片机和CPLD实现对输入信号的频率计数，单片机采用Ｃ语言，CPLD采用verilog语言。-MCU and CPLD count the frequency of the input signal, the microcontroller using the C language, CPLD verilog language.
verilog-example
- verilog实例，是开发cpld、fpga时参考程序，很实用-Verilog example, is the development of CPLD, FPGA reference procedures, it is practical
CPLD-Three-voting
- CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voti
cpld_ads7844_50M(9-24)
- 用ads7844采集数据，用cpld做时序控制，通过串口观察和记录采集结果，用verilog编写，通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
CPLD-code
- CPLD开发板实验代码，包括Verilog和VHDL源代码，原理图-CPLD development board experimental code, including Verilog and VHDL source code, schematics
digital-clock
- CPLD Verilog HDL实现数字钟-CPLD Verilog HDL digital clock
uart-code-(Verilog)
- uart 源码 Verilog CPLD -uart code Verilog CPLD
Cpld
- 本程序是用verilog语言在CPLD上实现智能小车控制部分，并通过并行通信，实现与单片机的通信。-This program is to control the robot car,and comunication with the C8051FXX by the Parallel communication.
beep
- fpga cpld verilog hdl 语言 代码程序 beep 控制
CPLD_LED
- fpga cpld verilog hdl 语言 代码程序 led 控制
I2C
- fpga cpld verilog hdl 语言 代码程序 beep 控制
switch
- fpga cpld verilog hdl 语言 代码程序 开关 控制
seg7_8
- fpga cpld verilog hdl 语言 代码程序 数码管 控制
RESOLVER
- 旋变位置信号的监测，cpld verilog-Monitoring resolver position signal, cpld verilog
Verilog_prj
- 特权同学的CPLD学习版 Verilog和VHDL代码。含有仿真文件。-Learning Edition privileged students CPLD Verilog and VHDL code. Contains simulation files.
HL-340_xp
- quartus verilog FPGA/cpld 例程 verilog简单例程-quartus verilog FPGA/cpld verilog simple routine routines
sed
- CPLD数码管程序,详细的7段式数码管程序。-CPLD verilog program
0001_EPM3064最小系统模块_带JTAG_LED_2mm插针
- EMP3064的开发板板，原理图，verilog例子，板子说明，规格书，全套资料(EMP3064 development board, schematics, Verilog examples, board instructions, specifications, a full set of information)