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D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
d
- VHDL的D触发器,简明了
d
- d 触发器 简单的d触发器，上传仅供参考，望各位多多指教。
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
dff_clk
- 简单的D触发器的Verilog描述及，仿真波形-A simple D flip-flop in Verilog descr iption and simulation waveforms
74hc74
- 带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
d-flip
- 同步复位的D 触发器，该触发器有一个数据输入端D，时钟输入端CLK，清 零输入端CLR，数据输出端Q。CLR为1时，触发器复位-Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
my_reg
- D触发器，Verilog实现，配有实验说明文档。-D flip-flop, Verilog implementation, with experimental documentation.
D_latch
- 周立功 ACTEl FPGA做的一个D触发器程序-ZLG ACTEl FPGA program to do a D flip-flop
D
- 利用时钟信号实现同步D触发器的功能的vhdl代码-Using D flip-flop clock signal to synchronize the function of vhdl code
D
- 这是一个用VHDL实现一个D触发器的程序-This is a VHDL implementation of a D flip-flop process
D
- 数字电子电路中的D触发器的VHDL的实现-Digital electronic circuits in the D trigger VHDL realization
D
- 此程序为以D触发器为基础的电路连接图，用于证明与学习阻塞赋值与非阻塞赋值的区别，已仿真成功。-This procedure is based on the D flip-flop circuit connection diagram for the proof and the blocking assignments and nonblocking assignments to learn the difference between the simulation has been succes
D-flip-flop
- Verilog的简单D触发器设计-Simple D flip-flop in Verilog design
D
- FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop
The-D-flip-flop
- D触发器的Verilog硬件语言实现，开发环境是ModelSim-The D flip-flop of the Verilog hardware language development environment is ModelSim
D-flip-flop
- D 触发器的描述 寄存器的行为 描述 -D flip-flop registers describe the behavior described in the behavior described register
D-trigger
- FPGA/CPLD开发，基于VHDL语言的D触发器的实现-FPGA/CPLD development, based on VHDL implementation of the D flip-flop
Y_0D
- 带同步置1、异步清0的D触发器。详细的讲解，易懂。(D flip-flop with synchronous 1 and asynchronous clear 0. Detailed explanation, easy to understand.)