搜索资源列表
DE2_70_VIDEO_V1.2.0
- daltera友晶的e2-70视频处理源码，包含整个工程，可以下载学习-de2-70videoprocessing source code, including theentireproject, you candownload learning
OV5620
- ov5620摄像头采集并显示，基于DE2的开发板。-ov5620 camera capture and display, based on the DE2 development board.
OV7670_VGA
- 采用OV7670摄像头采样视频数据通过FPGA DE2开发板用VGA显示在显示屏上。-Using OV7670 camera video data sampled by FPGA DE2 development board with a VGA display on the screen.
clock2
- 基于Verilog HDL及DE2开发板的数字钟设计，使用Verilog HDL实现-Based on Verilog HDL and DE2 development board of the digital clock design, use Verilog HDL to implement
VGA_DATA
- Create VGA module using VHDL on Altera DE2. It is better if you understand the full theory of VGA.
DE2_115_TV
- This an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115-This is an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115
pingpong
- 使用Verilog HDL 实现了一个桌球游戏，并在DE2开发板上验证通过。-Use Verilog HDL to achieve a table tennis game, and through the verification on the DE2 development board.
Fisheye_Correction_v2
- 基于DE2-115的鱼眼畸变矫正verilog实现，具有拍照即存储照片功能，通过VGA输出实时的矫正后的图像-Based DE2-115 fisheye image distortion correction verilog realized that store photos with a camera function, real-time via the VGA output after correction
morsecode
- 用DE2板，用SW0 到1表示想要的字母，KEY1运行，红灯显示对应的摩斯码，KEY0重置-With DE2 board with SW0 to 1 indicates the desired letter, KEY1 running red lights display the corresponding Morse code, KEY0 reset
DE2_LED_sm
- 驱动DE2—70开发板上数码管，并设计了一个时钟计数器，时钟计数时，分，秒。-DE2 70 development board driver digital tube, and designed a clock counter, clock count, minutes, seconds.
DE2devboard_audio_examples_DSPBv81
- dsp BUILDER EXAMPLE ON ALTERA DE2 BOARD
DE2_NIOS_DEVICE_LED
- DE2 利用nios ii控制LED灯 demo实例 实测可用 欢迎下载-DE2 control LED lights use nios ii demo instance of actual usable welcome to download
elevator
- 用DE2的板子实现电梯的基本功能，如上下楼，在电梯内按楼层，1至4楼的人上下楼等功能-using the DE2 board to being a elevator.
A201001-2186
- 频谱分析仪是信号处理研究领域必不可少的工具。现有的基于快速傅利叶变换的频 谱分析仪能对线性的平稳的信号进行有效分析，但难以分析出非线性非平稳信号的瞬时频率 能量变化情况。针对此问题，本文设计了基于希尔伯特黄变换的频谱分析仪，能够对非平稳 信号进行有效分析。所设计系统以DE2-FPGA开发板为硬件平台，结合了NiosII的软核处 理器加以实现，可对采集的外部信号进行希尔伯特黄变换，得到信号的时间-频率-能量三维 谱，并可在VGA上实时显示出来。系统测试结果表明，所设计频谱分析仪
PLL_1
- Phase lock loop generation for vhdl (DE2 board)
IMAGE_ROTATION_v2
- 基于DE2-115开发板，采用控制波动开关 SW[2:0]实现图像±45°，±90°旋转及VGA显示-Implementing the rotation of image based on DE2-115 board. Used switch SW[2:0] to control the orientation of rotating image(±45°&±90°).
hex7segb
- Implimentation of the switches and 7 segment display bit counter on an Altera DE2 baord via VHDL code on the Cyclone II FPGA
LCD
- LCD的循环输出，在Quartus二的环境下进行开发，DE2-70的开发板，用VHDL语言编写-LCD de xúnhuán shūchū, zài Quartus èr de huánjìng xià jìnxíng kāifā,DE2-70 de kāifā bǎn, yòng VHDL yǔyán biānxiě
Altera_Audio
- 针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。-The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.
AudioSubSystemStereo
- DE2-115 AUDIOSUBSSTEM