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codeofvhdl2006
- 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
dff
- 关于DFF的FPGA实现，有VHDL源码-On the DFF of the FPGA implementation, there are VHDL source code
code
- 用dff方法实现二分频，行为描述实现二分频，二分频，投票代码，有限状态机-Dff method used to achieve two-way, behavioral descr iptions to achieve two-way, two-way, voting codes, finite state machine
DFF
- 一个可用的D触发器 里面还有波形 本人仿真过 可用-DFF
sram
- 实现单端口SRAM，地址4比特即一共16个寄存单元，数据4比特说明每个单元有四个寄存器，一共64个D-Single-port SRAM, 4-bit address that is a total of 16 storage units, data 4-bit instructions each unit has four registers, a total of 64 DFF
dff
- 嵌入式实时操作系统ucos_ii中文版-Embedded real time operating system ucos_ii Chinese
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
d_ff
- 带置位、清零使能的D触发器以及同步清零D触发器、异步清零D触发器-VHDL，DFF
DFF
- actel fpga D触发器 verilog描述-pdf actel fpga d
dff
- this the code for d flipflop -this is the code for d flipflop
dff
- D触发器，以模块输入形式，仿真得到时序图、功能图-The simulation example of dff
Dff
- D 触发器，数字电路中最基本的逻辑单元之一。很实用的程序例子-D flip-flop, one of the basic logics in the digital design, an instance of a Sequential VHDL codes
DFF_div2
- 基于DFF的2分频器，verilog环境， 门级描述-based on DFF counter 2, gate level
ComparatorTestVersion
- 基於wire方式設計的補償器,但需外接DFF依照同學想做幾階的可在進行外加,Z^-1 需2個 Z^-2 3個依此類推.僅提供實做參考,實際參數需自行設計-Based on wire mode compensator design, but need to add DFF in accordance with the order of a few students want to be carrying plus, Z ^-1 need two Z ^-2 3 one, and so on. Pr
DFF
- D flip-flpo design using VHDL codes
UDP
- UDP of Dff and mux. COntains test bench also
DFT
- Insert scan chain to test DFF| DFT |
FIFO Design Using Verlilog
- DFF with fifo concepts
DFF
- a vhdl source code for dff