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shifter
- 移位运算器SHIFTER 使用Verilog HDL 语言编写,其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路,在J钟信号到来时状态产生变化, CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态,具有数据装入、数据保持、循环右移、带进位循环右移,循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入,通过键5 产生高低电平M 控制工作模式, M=l 时带进位循环移位,由键8 控制CO 为允许带进位移位输入,由键7 控制:S 控制移位模式0-3 ,由键6 控制
MCU_Digital_Clock
- 单片机的数字钟设计,毕业设计,带Protel图,源代码用proteus软件仿真通过,附有毕设论文-Microcontroller digital clock design, graduate design with Protel map, the source code through the use proteus software simulation, with a Bi-based papers
bit-clock
- m sure you ve seen analog clocks, digital clocks and maybe even binary clocks! Traditionally, analog clocks (or watches) display time by a continuous motion of two (hour, minute) or three (second) rotating pointers pointing to numbers arrayed on a c
m
- 基于51单片机数码管的电子时钟,时间精确-Based on 51 single chip microcomputer digital tube digital clock, time accurately
RANGEN
- 2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码,verilog编写;包括了M序列及同步时钟的提取等所有程序。-2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-seq
m
- 南工程数电课程设计多功能数字钟优秀设计 所有原理图 电路图 实际接线图都在哦-Southern electrical engineering curriculum design number of outstanding design multifunction digital clock schematic circuit diagram of all the actual wiring diagram are oh
16qam
- 一个16QAM数字调制电路,包括时钟生成电路,m伪随机序列生成电路,串并转换电路,电平映射电路、载波信号发生电路、ASK幅度调制电路及加法器(A 16QAM digital modulation circuit, including clock generation circuit, m pseudo-random sequence generation circuit, serial parallel conversion circuit, level mapping circuit, car