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EX2_ASM
- 汇编程序所在目录ex2_asm 。 C 语言程序所在目录ex2_c 。 在CC2000 中的操作如下： 1. Project->Open ，打开该目录中的工程文件。 2. Project->Rebuild ALL, 编译链接 3. File->Load Program 4. Debug->GO Main 5. Debug->RUN （快捷键F5） 即可看到最边上一个LED 周期性的闪亮。灯的闪烁频率由软件中的定时器
AD_TLC5510
- 用TLC5510实现高速A/D采样。用状态机的方法实现，在状态st0，给A/D一个采样时钟adck的上升沿，同时锁存A/D的输出-Using TLC5510 high-speed A/D sampling. The method used to achieve a state machine, in the state st0, to A/D sampling clock adck a rising edge of, and latched A/D output
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
zonggongcheng
- 三个结合起来的D触发器的vhdl，分别是电平触发，上升沿出发和下降沿出发。-Combining the three D flip-flop vhdl, respectively, trigger level, rising and falling edge start start.
EDGELAP
- Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
sobel_verilog
- Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
lab2
- D-type storage elements The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops. Write a VHDL file that instantiates the th
password
- verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the
verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
12864dededechengxu
- /*------------------------------------------ lcd12864液晶显示驱动实 ---------------------------------------------- ----------------------------------------------- RS:D/I=H,表示DB7～DB0为显示数据 D/I=L,表示DB7～DB0为显示指令数据 -----------------------------------
ADC
- 3．A/D程序设计与电路仿真 通过AD对外部电压进行AD采样，然后利用SPI接口对采样回来的数据进行显示，并将转换结果通过UART发给上位机进行显示。 首先设置需要显示的数组，使用PINSEL0、PINSEL1寄存器设置串口0的连接端口，使用IO0DIR设置74HC595的控制口，初始化串口0，使用U0LCR、U0DLM、U0DLL、U0LCR寄存器设置波特率，初始化SPI接口，设置SPI的时钟分频、接口模式。 其次对ADC模块进行设置，通过移位设置寄存器ADCR选择通道0，设置转换
Lab11_flipflopcs
- 带有置位和清零端的边沿D触发器的设计与实现.带有置位和清零端的边沿D触发器的逻辑图，本实验中用Verilog语句来描述。-Design and implementation of an edge D flip-flop with set and reset end. Logic diagrams with edge D flip-flop with set and reset the end of the Verilog statement, used in this experiment to
Dlatch3
- 基于VHDL的触发器设计。 由一个电平触发的D触发器构成的上下边沿触发器。-Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
src
- 同步异步复位、上升沿触发D触发器-Synchronous asynchronous reset, rising edge triggered D flip-flop
Dchufaqi
- VHDL实现D触发器包括上升沿触发，下降沿触发，时钟触发-VHDL realize D flip-flop including rising along the trigger, falling edge trigger, triggered the clock
d
- 图像边缘检测，提取图像边缘部分，显示灰度值图像-Image Edge Detection
shft
- 含同步并行预置功能的8位移位寄存器。工作原理 当CLK的上升沿到来时进程被启动，如果这时预置使能LOAD为高电平，则将输入端口的8位二进制数并行置入移位寄存器中，作为串行右移输出的初始值；如果LOAD为低电平，则执行语句： reg8（6 downto 0）< reg8(7 downto 1)-8 bit shift register with synchronous parallel preset function. The principle of work when the ri