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  1. equlizer

    0下载:
  2. 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:23727
    • 提供者:陈为
  1. DLMS

    0下载:
  2. DLMS equalizer for qam
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:3378
    • 提供者:cyberia
  1. adaptive_lms_equalizer_latest.tar

    0下载:
  2. In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:13862
    • 提供者:Arun
  1. fir_9222_sopc

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  2. 基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-20
    • 文件大小:5911361
    • 提供者:z
  1. IterativeDecodingofBinary

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  2. In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1515947
    • 提供者:suresh
  1. VerilogLangRefManual

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  2. Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1283063
    • 提供者:suresh
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