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top_FFT
- 128k点流水FFT算法的IP核设计，顶层文件，一共13级流水-128k-point FFT algorithm running water IP core design, top-level file, a total of 13 water
fft_512
- 采用Xilinx提供的VHDL FFT ip核实现512点FFT，可以实现使能控制、时钟控制等功能-Using Xilinx provides VHDL FFT ip core to achieve implementation of 512 points FFT, with enable control, clock control and other functions
vlfft
- 基于8核DSP的超大数据量FFT的分解算法和并行实现源码，语言为嵌入式C，内部有配置说明。-Based on 8 core DSP of the large data volume of FFT decomposition algorithm and parallel implementation source code, language for embedded C, the internal configuration.
pipelined_fft_256
- pipelined fft/ifft 256 point ip core
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
vlfft
- 基于TMS320C66x系列DSP的超大规模FFT实现，可作为《TMS320C66x KeyStone架构 多核DSP入门与实例精解》书中5.3小节的例程使用。-Based on VLSI FFT TMS320C66x series DSP implementation, as a routine use TMS320C66x KeyStone architecture and multi-core DSP Starter instance fine solution, the book s
fft_analyze
- 利用Altera的IP核，实现FFT算法使用信息流模式读写，使用SignalTap II嵌入式逻辑分析仪观察信号，A/D只要是并行的8位芯片都可以。-Achiving FFT by using Altera IP Core,you can observe the signal by the embedded logic analyzer Signal Tap II,as for A/D device, it s suitable for a parllarel 8 bits A/D device