搜索资源列表
myfifo
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_syn
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_wave0
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_wave1
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
FIFOinterface
- fifo(8):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
fifotop
- 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
gencontrol
- 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
FIFO
- VHDL code for first in first out register
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
fifo
- first in first out VHDL code
FIFO_Buffer
- Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
fifo_test.v.tar
- code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
asymmetric_fifo
- 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB