搜索资源列表
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
DW_ahb_dmac_sbiu
- designware提供的dmac slave接口硬件描述语言-designware provide the source code verification VIP FIFO
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
small_fifo
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小，易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
SYNC_FIFO
- its simple fifo.which is used to first in first out for vhdl source code
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont
p_t_s_422
- 应用于422串行通信中并行数据转串行的代码，可以结合fifo使用-422 serial communication used in parallel data to serial code, can combine the use of fifo
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
simpleFIFO
- FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware descr iption language source code
XR16M2550
- XR16M2550是一款高性能，具有16字节收发FIFO的异步全双工UART芯片，具有两路完全独立的UART通道。本资料包含完整的测试代码（ADS 1.2环境），中文应用文档，电路原理图，PPT讲解稿等。-XR16M2550 is a high-performance, with 16-byte receive FIFO, asynchronous full-duplex UART chip, with two-way completely independent UART channels.
X28xx_sourcecode
- word文档内有九个例子源程序： 例1、初始化锁相环及外设时钟函数 例2、.cmd格式文件举例 例3、定时器中断应用举例 例4、利用事件管理器输出多种频率的正弦信号输出例程 例5、SPI和DAC TLV 5617接口例程 例6、CAN总线消息发送例程 例7、使用FIFO缓冲发送数据 例8、使用FIFO缓冲接收数据 例9、ADC应用举例 -this word document includes nine examples of source
SFIFO
- 可以实现任意位的同步FIFO的verilog实现-the verilog code of a common SFIFO
vhdlfifo1
- fifo - source code for first in first out(fifo) using VHDL
vhdlfifo
- fifo- source code for fifo using VHDL
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
uart
- Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup
fallthrough_small_fifo_v2
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short
syn_fifo
- 很好的同步FIFO设计代码，和大家分享一下，多多交流，不是我自己写的-Good synchronous FIFO design code, and share with you some more exchanges, not my own writing
FPGA_test_frequency
- 基于FPGA的高精度测量频率的程序，里面有FIFO的子函数，代码完整-FPGA-based high-precision measurement of the frequency of the procedure, there are FIFO, Functions, code integrity