This file if about DPram based fifo storage... wirte and read in both ports

I ve implemented what oi believe to be a very usefull and easy way to understand the FIFO queue using a DPRAM

本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by

FIFO queiue using DPRAM goog project