搜索资源列表
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
SYNC_FIFO
- its simple fifo.which is used to first in first out for vhdl source code
simpleFIFO
- FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware descr iption language source code
fifo89
- 一个先进先出缓冲器的vhdl源代码，深度是8，宽度是9位。-A FIFO CODE IN VHDL.
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
fifo
- fifo in vhdl file code
aFifo
- it is a vhdl source code for FIFO
61i_async_fifo_v5_1_vhdl
- VHDL Code for FIFO+coregen v5.0
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
asdhbja
- 异步FIFO源代码 vhdl基于FPGA的设计，绝对值得一下，非常不给力的20 个字-vhdl code of asynchronous FIFo
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
VHDL-8bitFIFO
- FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit M
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
VHDL_RAM_FIFO_ROM
- VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)