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48_order-FIR-filter-with-8-folder
- 该代码是设计一个48阶FIR滤波器的文档,该设计方案主要运用了数字信号处理VLSI实现中的折叠的方式。-The code is a 48-order FIR filter design document, the main use of the design of VLSI implementation of digital signal processing in the way of folding.
Lab0501-FIR
- ICETEK-VC5509-A FIR滤波器设计源代码-ICETEK-VC5509-A FIR filter design source code
fir
- 定点fir滤波设计,汇编级优化代码,可用于学习ADI公司的DSP的例子,非常实用-Sentinel fir filter design, the compilation of code-level optimization can be used to study ADI
FIR-h(t)
- 利用窗函数法设计FIR滤波器,给出其抽样响应。程序中调用了子程序window。-Using window function design FIR filter, given in response to its sample. Calling the subroutine program window.
FIR
- FIR滤波器设计,里面包含FIR和IIR等 应该比较全吧-FIR filter design, which contains FIR and IIR and so it should be more wide
wendang
- 关于数字信号处理的几篇PPT文档(IIR/FIR滤波器设计等),适合数字信号处理入门学习-Digital signal processing on several PPT files (IIR/FIR filter design, etc.), suitable for digital signal processing Introduction to learning
FIR
- 基于FPGA的FIR滤波器设计思想,里面有很好的算法供大家参考-FPGA-based FIR filter design ideas, there are very good for your reference algorithm
FIR
- 线性缓冲区FIR滤波器设计,可利用MATLAB产生系数,利用CCS开发环境,调试成功!-FIR filter design for linear buffer can be generated using MATLAB coefficient, the use of CCS development environment, debugging success!
65jie
- 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点,但是要占用大量的资源。在多阶数的亚高频系统设计中,使用并行结构并不合算,但亚高频系统需要较高的处理速度,而串行架构往往达不到要求,因此,结合串并这两种设计方法的长处,在使用较少的硬件资源的同时实现了较高的处理速度,这里说明一种65阶八路并行、支路串行FIR滤波器的设计(实际使用了1个乘法器,8个乘累加器,一个累加器)。-String and FIR filter design: parallel FIR filter with a
FIR_filters_Xilinx
- FIR filter design method using Xilinx FPGA platform.
FIR
- fir filter design using vhdl codes
AM
- FIRPM公园,麦克莱伦最佳equiripple FIR滤波器的设计。乙= FIRPM(不适用,女,甲)返回一个长度为N +1线性相位(真实,对称系数)FIR滤波器具有最佳逼近到所需的频率响应的F和描述在极小极大意义的。F是成对频带边缘载体,以递增0和1之间秩序。 1对应于奈奎斯特频率或采样频率的一半。至少有一个频段必须有一个非零宽度。 A是一个真正的载体,作为F的指定由此得到的滤波器的频率响应所需的幅度B相同大小- FIRPM Parks-McClellan optimal equirippl
fir-c2h
- 基于fpga的fir滤波器的设计 非常好,谢谢大家分享-fir filter design base on fpga it is very good
fir
- 数字电路设计中的,fir滤波器设计,我做的是8位宽的,利用vhdl实现,附带了完整的代码,报告,我没有对我的信息进行删除,是希望大家能够诚实的利用这个代码,提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
FIR-filter-using-fpga-design
- 基于FPGA的高阶FIR滤波器设计4有matlab设计步骤 4.3更详细 第六章量化系数实例-FIR using FPGA ,QuartusII software
fir-filter-design-using-fpga-with-MAX-Plus2
- 基于FPGA的高阶FIR滤波器设计用max-plus -II软件仿真-fir filter using fpga with max-plusII
fir-filter-design-and-implementation
- 简单正确的fir滤波器设计与实现,帮助我们更好的设计更复杂的滤波器-Simple and correct fir filter design and implementation, to help us better design more complex filter
FIR-filter-design-LP-triangular-design
- FIR filter design LP triangular design
LP-FIR-filter-design-rectangular-window
- LP FIR filter design rectangular window
fir filter design
- FIR FILTER DESIGN IN VERILOG ON FPGA