搜索资源列表
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
FLIP
- ATMEIL FLIP下载线电路图,这个电路也兼容NXP单片机的在线下载线-Download ATMEIL FLIP-line circuit, the circuit is also compatible with the online download NXP Single Chip Line
jkff
- JK flip-flop is implemented using VHDL
vhdl_jk
- 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
JK_F_F
- This a VHDL code for J-K flip flop-This is a VHDL code for J-K flip flop
jkandTflipflop
- this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
srandDflipflop
- this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
74hc74
- 带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
d-flip
- 同步复位的D 触发器，该触发器有一个数据输入端D，时钟输入端CLK，清 零输入端CLR，数据输出端Q。CLR为1时，触发器复位-Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
main
- 1664双色点阵屏的翻页钟程序，欢迎大家下载，谢谢诶！-1664 two-color dot-matrix screen flip clock program, are welcome to download, thank you ah!
D_latch
- 周立功 ACTEl FPGA做的一个D触发器程序-ZLG ACTEl FPGA program to do a D flip-flop
vhdl-code-for-jk-flip-flop
- vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
D-flip-flop
- Verilog的简单D触发器设计-Simple D flip-flop in Verilog design
The-D-flip-flop
- D触发器的Verilog硬件语言实现，开发环境是ModelSim-The D flip-flop of the Verilog hardware language development environment is ModelSim
D-flip-flop
- D 触发器的描述 寄存器的行为 描述 -D flip-flop registers describe the behavior described in the behavior described register
JK-flip-flop
- 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language
D-type-flip-flop
- 设计一个D型触发器，输入CK（时钟信号, ↑表示上升沿时刻），D（数据），Clear端（“0”时清零），输出Q-Design of a D-type flip-flop, the input CK (clock signal, ↑ indicates rising time), D (data), Clear end (" 0" is cleared), the output Q
d-Flip-Flop
- D flip flop and some other codes added together recomended use is adding layer not use in a single bench